SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 113

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

7.1.12
7.1.13
7.2
Datasheet
Register Name: TIR
Register Description: Transmit Interrupt
Access: Read/Write
Register Name: TICR
Register Description: Transmit Interrupting Channel
Access: Read/Write
TxIreq
Bit 7
Bit 7
X
Bit
2
1
0
Transmit Interrupting Channel Register
See
Transmit Interrupt Register
See
Virtual Registers
The CD1284 has two operational contexts:
This special set of registers is called Virtual because they are only available to host access and valid
during this service-acknowledge context. At all other times, their contents are undefined and must
not be written to by host software.
The use of Virtual registers and context switching allows the CD1284 to maintain all channel-
specific information. To access the registers pertinent to the channel being serviced, it is not
necessary for the host to make any changes to the device registers.
The service-acknowledge context can be entered in two ways: 1) by activating one of the
SVCACK* input pins (hardware-activated); 2) by the host software when the contents of any one
of TIR, RIR, MIR, or PIR are copied into the CAR during a Poll-mode acknowledge cycle.
5.0
Service Request Modem: ‘1’ indicates request pending.
Service Request Transmit: ‘1’ indicates request pending.
Service Request Receive: ‘1’ indicates request pending.
Txbusy
Bit 6
Bit 6
discusses the differences between these two modes.
Section 7.1.5 on page
Section 7.1.6 on page
Normal: Allows host access to most registers and any channel
Service-acknowledge: Allows host access to some registers specific to the channel requesting
service.
X
Txunfair
Bit 5
Bit 5
X
IEEE 1284-Compatible Parallel Interface Controller — CD1284
109, the description of the MICR, for details on the TICR.
110, the description of the MIR, for details on the TIR.
Bit 4
Bit 4
X
1
Description
Bit 3
Bit 3
C1
0
Bit 2
Bit 2
C0
0
Bit 1
ch[1]
Bit 1
8-Bit Hex Address: 45
8-Bit Hex Address: 6A
X
Default Value: 10
Default Value: 00
Bit 0
ch[0]
Bit 0
Chapter
X
113