SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 46

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
Figure 7. Interrupt Generation Logic (Continued)
46
(PCISR[5])
NEGCH
Host has reversed the direction of the interface from ECP-
forward to ECP-reverse by driving nReverseRequest (nInit)
signal low.
A1284 signal
transition from
high-to-low, and
A1284(ZDR[3]) = 1
A1284 signal
transition from low-
to-high, and
A1284(ODR[3]) = 1
Host has changed the direction of the interface from ECP-
reverse to ECP-forward by driving nReverseRequest
(nInit) signal high.
(PCISR[4])
SIGCH
nInit signal
transition from
high to low, and
nInit(ZDR[2]) = 1
nInit signal
transition from
low-to-high, and
nInit(ODR[2]) = 1
(PCISR[3])
EPPAW
(PCISR[2])
DIRCH
HstBsy signal
transition from high-
to-low, and
HstBsy(ZDR[1]) = 1
HstBsy signal
transition from low-
to-high, and
HstBsy(ODR[1]) = 1
(PCISR[1])
IDREQ
HstClk signal
transition from
high-to-low, and
HstClk(ZDR[0]) = 1
(PCISR[0])
NINIT
HstClk signal
transition from low-
to-high, and
HstClk(ODR[0]) = 1
EPP address received
In Compatible mode, the
host has requested the
peripheral to re-initialize
itself (nInit went low).
on parallel port
(PCIER[0])
(PCIER[3])
(PFCR[4])
(PCIER[4])
Interface must be in COMPATIBLE MODE
when MANMD (PCR.7) is set or MANMD wil
have no affect
(PCR[7])
EPPAW
MANMD
INTEN
SIGCH
nInit
Datasheet
SIGCH
(PCISR[4])
EPPAW
(PCISR[3])
DIRCH
(PCISR[2])
NINIT
(PCISR[0])
PPORT
(PIR[6])