MAX11156ETC+ Maxim Integrated, MAX11156ETC+ Datasheet - Page 15

• Manufacturer Part Number: MAX11156ETC+
• Description: Analog to Digital Converters - ADC 18Bit 500ksps 5V SAR ADC w/Internal Ref
• Manufacturer: Maxim Integrated

Specifications of MAX11156ETC+

• Rohs: yes
• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 500 KSPs
• Resolution: 18 bit
• Input Type: Pseudo-Differential
• Snr: 94.6 dB
• Interface Type: SPI
• Operating Supply Voltage: 2.3 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TDFN-12
• Maximum Power Dissipation: 38.5 W
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1

MAX11156
Input Configuration Interface
An SPI interface clocked at up to 50MHz controls the
MAX11156. Input configuration data is clocked into the
configuration register on the falling edge of SCLK through
the DIN pin. The data on DIN is used to program the ADC
configuration register. The construct of this register is
illustrated in
the output interface mode, the reference mode, and the
power-down state of the MAX11156.
Table 4. ADC Configuration Register
Figure 4. Input Configuration Timing in CS Mode
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BIT NAME
Reserved
MODE
SHDN
REF
CNVST
SCLK
DIN
Table
BIT
7:6
5:4
2:0
3
4. The configuration register defines
t
SSCKCNF
DEFAULT
STATE
00
00
0
0
B7
0
t
HDINSCK
t
LOGIC
STATE
HSCKCNF
00
01
10
00
01
10
B6
11
11
1
0
1
0
CS Mode, No-Busy Indicator
CS Mode, with Busy Indicator
Daisy-Chain Mode, No-Busy Indicator
Daisy-Chain Mode, with Busy Indicator
Reference Mode 0. Internal reference and reference buffer are both
powered on.
Reference Mode 1. Internal reference is turned off, but internal reference
buffer powered on. Apply the external reference voltage at REFIO.
Reference Mode 2. Internal reference is powered on, but the internal
reference buffer is powered off. This mode allows for internal reference to
be used with an external reference buffer.
Reference Mode 3. Internal reference and reference buffer are both
powered off. Apply an external reference voltage at REF.
Normal Mode. All circuitry is fully powered up at all times.
Static Shutdown. All circuitry is powered down.
Reserved, Set to 0
B5
2
B4
3
Configuring in CS Mode
Figure 4
tion register when the MAX11156 is connected in CS mode
(see
The load process is enabled on the falling edge of CNVST
when SCLK is held high. The configuration data is clocked
into the configuration register through DIN on the next 8
SCLK falling edges. Pull CNVST high to complete the input
configuration register load process. DIN should idle high
outside an input configuration register read.
t
SDINSCK
Figure 6
B3
4
details the timing for loading the input configura-
with Internal Reference in TDFN
18-Bit, 500ksps, ±5V SAR ADC
and
B2
5
FUNCTION
Figure 8
B1
6
for hardware connections).
B0
7
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