MAX11156ETC+ Maxim Integrated, MAX11156ETC+ Datasheet - Page 21

• Manufacturer Part Number: MAX11156ETC+
• Description: Analog to Digital Converters - ADC 18Bit 500ksps 5V SAR ADC w/Internal Ref
• Manufacturer: Maxim Integrated

Specifications of MAX11156ETC+

• Rohs: yes
• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 500 KSPs
• Resolution: 18 bit
• Input Type: Pseudo-Differential
• Snr: 94.6 dB
• Interface Type: SPI
• Operating Supply Voltage: 2.3 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TDFN-12
• Maximum Power Dissipation: 38.5 W
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1

MAX11156
Figure 11. Multichannel CS Configuration Timing
Daisy-Chain, No-Busy Indicator Mode
The daisy-chain mode with no-busy indicator is ideally
suited for multichannel isolated applications that require
minimal wiring complexity. Simultaneous sampling of
multiple ADC channels is realized on the serial inter-
face where data readback is analogous to clocking a
shift register.
two MAX11156s configured in a daisy chain. The corre-
sponding timing is given in
A rising edge on CNVST completes the acquisition and
initiates the conversion. Once a conversion is initiated,
it continues to completion irrespective of the state of
CNVST. When a conversion is complete, the MSB is
presented onto DOUT and the MAX11156 returns to the
acquisition phase. The remaining data bits are stored
within an internal shift register. To read these bits out,
CNVST is brought low and each bit is shifted out on sub-
sequent SCLK falling edge. The DIN input of each ADC
in the chain is used to transfer conversion data from the
previous ADC into the internal shift register of the next
ADC, thus allowing for data to be clocked through the
multichip chain on each SCLK falling edge. Each ADC
in the chain outputs its MSB data first requiring 18 × N
clocks to read back N ADCs.
www.maximintegrated.com
CNVSTA(CS1)
CNVSTB(CS2)
ACQUISITION
DIN
SCLK
DOUT
t
SSCKCNF
t
CNVPW
Figure 12
CONVERSION
t
CONV
shows a connection diagram of
t
HSCKCNF
Figure
t
EN
13.
D17
1
D16
2
D15
3
t
DDO
t
SCLKL
t
SCLKH
In daisy-chain mode, the maximum conversion rate
is reduced due to the increased readback time. For
instance, with a 5ns digital host setup time and 3V inter-
face, up to four MAX11156 devices running at a conver-
sion rate of 279ksps can be daisy-chained.
Daisy-Chain with Busy Indicator Mode
The daisy-chain mode with busy indicator is ideally suited
for multichannel isolated applications that require minimal
wiring complexity while providing a conversion complete
indication that can be used to interrupt a host processor
to read data.
Simultaneous sampling of multiple ADC channels is real-
ized on the serial interface where data readback is analo-
gous to clocking a shift register. The daisy-chain mode
with busy indicator is shown in
MAX11156s are connected to a SPI-compatible digital host
with corresponding timing given in
A rising edge on CNVST completes the acquisition and
initiates the conversion. Once a conversion is initiated, it
continues to completion irrespective of the state of CNVST.
When a conversion is complete, the busy indicator is pre-
sented onto each DOUT and the MAX11156 returns to the
acquisition phase. The busy indicator for the last ADC in
t
ACQ
t
17
CYC
ACQUISITION
D1
t
t
SCLK
DIS
18
D0
with Internal Reference in TDFN
18-Bit, 500ksps, ±5V SAR ADC
19
D17
t
EN
20
D16
21
D15
Figure 14
Figure
Maxim Integrated │ 21
t
CNVPW
35
15.
D1
t
DIS
where three
36
D0