MAX11156ETC+ Maxim Integrated, MAX11156ETC+ Datasheet - Page 20

• Manufacturer Part Number: MAX11156ETC+
• Description: Analog to Digital Converters - ADC 18Bit 500ksps 5V SAR ADC w/Internal Ref
• Manufacturer: Maxim Integrated

Specifications of MAX11156ETC+

• Rohs: yes
• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 500 KSPs
• Resolution: 18 bit
• Input Type: Pseudo-Differential
• Snr: 94.6 dB
• Interface Type: SPI
• Operating Supply Voltage: 2.3 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TDFN-12
• Maximum Power Dissipation: 38.5 W
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1

MAX11156
Multichannel CS Configuration,
Asynchronous or Simultaneous Sampling
The multichannel CS configuration is generally used when
multiple MAX11156 ADCs are connected to an SPI-
compatible digital host.
diagram example using two MAX11156 devices.
shows the corresponding timing.
Asynchronous or simultaneous sampling is possible by
controlling the CS1 and CS2 edges. In
DOUT bus is shared with the digital host limiting the
throughput rate. However, maximum throughput is pos-
sible if the host accommodates each ADC’s DOUT pin
independently.
A rising edge on CNVST completes the acquisition,
initiates the conversion and forces DOUT to high
impedance. The conversion continues to completion
Figure 10. Multichannel CS Configuration Diagram
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MAX11156
Figure 10
DEVICE A
CNVST
SCLK
shows the connection
DOUT
DIN
Figure
Figure 11
10, the
MAX11156
DEVICE B
irrespective of the state of CNVST allowing CNVST
to be used as a select line for other devices on the
board. However, CNVST must be returned high before
the minimum conversion time for proper operation so
that another conversion is not initiated with insufficient
acquisition time and data correctly read out of the
device.
When the conversion is complete, the MAX11156 enters
the acquisition phase. Each ADC result can be read by
bringing its CNVST input low, which consequently outputs
the MSB onto DOUT. The remaining data bits are then
clocked by subsequent SCLK falling edges. For each
device, its DOUT will return to a high-impedance state
after the 18
high. This control allows multiple devices to share the
same DOUT bus.
CNVST
SCLK
with Internal Reference in TDFN
DOUT
18-Bit, 500ksps, ±5V SAR ADC
DIN
th
SCLK falling edge or when CNVST goes
CS2
CS1
CONFIG
DATA IN
CLK
DIGITAL HOST
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