MCIMX6U6AVM08AB Freescale Semiconductor, MCIMX6U6AVM08AB Datasheet - Page 139

• Manufacturer Part Number: MCIMX6U6AVM08AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Automotive and Infotainment Processorsr

Specifications of MCIMX6U6AVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 64 bit
• Maximum Clock Frequency: 800 MHz
• Instruction / Data Cache Memory: 32 KB
• Data Ram Size: 128 KB
• Data Rom Size: 96 KB
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: BGA 2240
• Interface Type: I2S, SSI, AC97, ESAI, UARTS, eCSPI, I2C, Ethernet, PWM, SJC, GPIO, KPP, SPDIF
• Memory Type: DDR3
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

4.11.20 UART I/O Configuration and Timing Parameters
4.11.20.1 UART RS-232 I/O Configuration in Different Modes
The i.MX 6Solo/6DualLite UART interfaces can serve both as DTE or DCE device. This can be
configured by the DCEDTE control bit (default 0 — DCE mode).
configuration based on the enabled mode.
4.11.20.2 UART RS-232 Serial Mode Timing
The following sections describe the electrical information of the UART module in the RS-232 mode.
Freescale Semiconductor
TXD_MUX
RXD_MUX
DCD
CTS
DTR
DSR
Port
RTS
RI
•
•
•
•
•
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Direction
Output
Output
Output
Input
Input
Input
Input
Input
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms, WL and BL, refer to Word Length (WL) and Bit Length
(BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
RTS from DTE to DCE
CTS from DCE to DTE
DTR from DTE to DCE
DSR from DCE to DTE
DCD from DCE to DTE
RING from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
Table 91. UART I/O Configuration vs. Mode
DTE Mode
Description
NOTE
Direction
Output
Output
Output
Output
Output
Input
Input
Input
Table 91
RTS from DTE to DCE
CTS from DCE to DTE
DTR from DTE to DCE
DSR from DCE to DTE
DCD from DCE to DTE
RING from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
shows the UART I/O
DCE Mode
Description
Electrical Characteristics
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