MT48H4M16LFB4-8 Micron Technology Inc, MT48H4M16LFB4-8 Datasheet - Page 27

• Manufacturer Part Number: MT48H4M16LFB4-8
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-8

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8:
Notes: 1-6; notes appear below table
NOTE:
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs
11. Does not affect the state of the bank and acts as a NOP to that bank.
1. This table applies when CKE
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allow-
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Deep Power-Down is power savings feature of this Mobile SDRAM device. This command is BURST TERMINATE when CKE is high and
Write (Auto
Row Active
Read (Auto
CURRENT
Precharge
Precharge
Disabled)
Disabled)
self refresh).
to be issued to that bank when in that state. Exceptions are covered in the notes below.
able commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Truth Table 3, and according to Truth Table 4.
each positive clock edge during these states.
DEEP POWER DOWN when CKE is low.
with auto precharge disabled.
STATE
Idle:
Row Active: A row in the bank has been activated, and
Read:
Write:
Precharging: Starts with registration of a PRECHARGE command and ends when
Row Activating: Starts with registration of an ACTIVE command and ends when
Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when
Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when
Any
Idle
Truth Table 3 – Current State Bank n, Command to Bank n
The bank has been precharged, and
in progress.
A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
the idle state.
in the row active state.
has been met. Once
t
be in the all banks idle state.
Once
will be in the idle state.
CS#
RP has been met. Once
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
t
MRD is met, the SDRAM will be in the all banks idle state.
RAS# CAS#
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
n-1
was HIGH and CKE
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
t
RP is met, the bank will be in the idle state.
t
RP is met, the bank will be in the idle state.
WE# COMMAND (ACTION)
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
n
is HIGH (see Truth Table 2) and after
t
RP has been met.
t
RCD has been met. No data bursts/accesses and no register accesses are
27
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t
t
RCD is met. Once
RP is met. Once
t
RC is met. Once
t
XSR has been met (if the previous state was
t
RP is met. Once
t
RP is met, the bank will be in
t
MOBILE SDRAM
RCD is met, the bank will be
t
RC is met, the SDRAM will
©2003 Micron Technology, Inc. All rights reserved.
t
MRD has been met.
t
RP is met, all banks
64Mb: x16
NOTES
11
10
10
10
10
10
10
7
7
8
8
9
8
9
t
RP