EPC4QI100 Altera, EPC4QI100 Datasheet - Page 112

• Manufacturer Part Number: EPC4QI100
• Description: IC CONFIG DEVICE 4MBIT 100-PQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC4QI100

• Programmable Type: In System Programmable
• Memory Size: 4Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-2189

4–22 Chapter 4: Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 4–20. EPC1, EPC2 and EPC1441 Pin Functions During Configuration (Part 2 of 3)
Configuration Handbook (Complete Two-Volume Set)
nCS
nCASC
nINIT_CONF
TDI
TDO
Pin Name
PDIP
8-Pin
N/A
N/A
N/A
4
6
(1)
Pin Number
20-Pin
PLCC
12
13
11
9
1
TQFP
32-Pin
10
15
16
13
28
(2)
Input
Output
Open-Drain
Output
Input
Output
Pin Type
Chip select input (active low). The nCS pin connects
to the CONF_DONE of the FPGA.
A low input allows DCLK to increment the address
counter and enables DATA to drive out. If the EPC1
or EPC2 is reset (OE pulled low) while nCS is low,
the device initializes as the master device in a
configuration chain. If the EPC1 or EPC2 device is
reset (OE pulled low) while nCS is high, the device
initializes as a slave device in the chain.
The nCS pin has an internal programmable 1-k
resistor in EPC2 devices. If internal pull-up resistors
are use, external pull-up resistors should not be used
on these pins.The internal pull-up resistors can be
disabled through the Disable nCS and OE pull-ups
on configuration device option.
Cascade select output (active low).
This output goes low when the address counter has
reached its maximum value. When the address
counter has reached its maximum value, the
configuration device has sent all its configuration
data to the FPGA. In a chain of EPC1 or EPC2 devices,
the nCASC pin of one device is connected to the nCS
pin of the next device, which permits DCLK to clock
data from the next EPC1 or EPC2 device in the chain.
For single EPC1 or EPC2 devices and the last device
in the chain, nCASC is left floating.
This pin is only available in EPC1 and EPC2 devices,
which support data cascading.
Allows the INIT_CONF JTAG instruction to initiate
configuration. The nINIT_CONF pin connects to the
nCONFIG of the FPGA.
If multiple EPC2 devices are used to configure a
FPGA, the nINIT_CONF of the first EPC2 pin is tied
to the FPGA’s nCONFIG pin, while subsequent
devices' nINIT_CONF pins are left floating.
The INIT_CONF pin has an internal 1-k pull-up
resistor that is always active in EPC2 devices.
This pin is only available in EPC2 devices.
JTAG data input pin. Connect this pin to V
JTAG circuitry is not used.
This pin is only available in EPC2 devices.
JTAG data output pin. Do not connect this pin if the
JTAG circuitry is not used.
This pin is only available in EPC2 devices.
© December 2009
Description
Altera Corporation
Pin Information
CC
if the