EPC4QI100 Altera, EPC4QI100 Datasheet - Page 96

• Manufacturer Part Number: EPC4QI100
• Description: IC CONFIG DEVICE 4MBIT 100-PQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC4QI100

• Programmable Type: In System Programmable
• Memory Size: 4Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-2189

4–6 Chapter 4: Configuration Devices for SRAM-Based LUT Devices Data Sheet
Device Configuration
Figure 4–2. Altera FPGA Configured Using an EPC1, EPC2, or EPC1441 Configuration Device
Notes to
(1) For specific details about configuration interface connections refer to the FPGA family chapter in the
(2) The nINIT_CONF pin (available on EPC2 devices) has an internal pull-up resistor that is always active. This means an external pull-up resistor
(3) EPC2 devices have internal programmable pull-up resistors on OE and nCS. If internal pull-up resistors are used, external pull-up resistors should
Configuration Handbook (Complete Two-Volume Set)
is not required on the nINIT_CONF/nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If
nINIT_CONF is not used or not available, nCONFIG must be pulled to V
not be used on these pins. The internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
Figure
4–2:
1
The EPC1, EPC2, and EPC1441 devices store configuration data in its EPROM array
and serially clock data out using an internal oscillator. The OE, nCS, and DCLK pins
supply the control signals for the address counter and the DATA output tri-state buffer.
The configuration device sends a serial bitstream of configuration data to its DATA
pin, which is routed to the DATA0 input of the FPGA.
The control signals for configuration devices (OE, nCS, and DCLK) interface directly
with the FPGA control signals (nSTATUS, CONF_DONE, and DCLK, respectively). All
Altera FPGAs can be configured by a configuration device without requiring an
external intelligent controller.
An EPC2 device cannot configure FLEX 8000 or FLEX 6000 devices. Refer to
on page 4–2
devices.
Figure 4–2
configuration device and the Altera FPGA. For specific details about configuration
interface connections, including pull-up resistor values, supply voltages and MSEL
pin setting, refer to the appropriate FPGA family chapter in the
Handbook.
The EPC2 device allows the user to begin configuration of the FPGA via an additional
pin, nINIT_CONF. The nINIT_CONF pin of the EPC2 device can be connected to the
nCONFIG of the FPGA, which allows the INIT_CONF JTAG instruction to begin FPGA
configuration. The INIT_CONF JTAG instruction causes the EPC2 device to drive
nINIT_CONF low, which in turn pulls nCONFIG low. Pulling nCONFIG low on the
n
MSEL
shows the basic configuration interface connections between the
FPGA
for the configuration devices that support FLEX 8000 and FLEX 6000
CONF_DONE
nSTATUS
nCONFIG
DATA0
DCLK
nCEO
nCE
N.C.
GND
V
CC
(3)
V
CC
(2)
CC
either directly or through a resistor.
V
CC
(3)
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
Configuration
Device
Configuration
nCASC
© December 2009
(Note 1)
N.C.
Configuration
Handbook.
Device Configuration
Altera Corporation
Table 4–2