NCP1081DER2G ON Semiconductor, NCP1081DER2G Datasheet - Page 15

• Manufacturer Part Number: NCP1081DER2G
• Description: IC CONV CTLR POE-PD 40W 20-TSSOP
• Manufacturer: ON Semiconductor
• Type: Power over Ethernet Switch (PoE)r

Specifications of NCP1081DER2G

• Applications: Remote Peripherals (Industrial Controls, Cameras, Data Access)
• Internal Switch(s): Yes
• Current Limit: 1.1A
• Voltage - Supply: 0 V ~ 57 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP Exposed Pad, 20-eTSSOP, 20-HTSSOP
• Output Voltage: 9 V
• Switching Frequency: 250 KHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Output Power: 40 W
• Input Voltage: 57V
• Supply Current: 510mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Duty Cycle (%): 80%
• Uvlo: 38V
• Frequency: 500kHz
• Svhc: No SVHC (20-Jun-2011)
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DC−DC Converter Controller
Internal VDDH and VDDL Regulators and Gate Driver
voltage to a 9 V output on the VDDH pin. VDDH supplies
the internal gate driver circuit which drives the GATE pin
and the gate of the external power MOSFET. The NCP1081
gate driver supports an external MOSFET with high Vth and
high input gate capacitance. A second LDO regulator steps
down the VDDH voltage to a 3.3 V output on VDDL. VDDL
powers the analog circuitry of the DC−DC controller and
nCLASS_AT blocks. Moreover it can provide current to
light a LED connected on the nCLASS_AT pin.
regulators include power−on−reset (POR) detectors which
prevent the DC−DC controller from operating when either
VDDH or VDDL is too low. In addition, an over−voltage
lockout (OVLO) on the VDDH supply disables the gate
driver in case of an open−loop converter with a
configuration using the bias winding of the transformer (see
Figure 4).
VPORT reaches the Vuvlo_on threshold.
Error Amplifier
internal error amplifier of the NCP1081 and the internal
1.2 V reference voltage regulate the DC−DC output
voltage. In this configuration, the feedback loop
compensation network should be inserted between the FB
and COMP pins as shown in Figures 3, 4 and 5.
The NCP1081 implements a current mode DC−DC converter controller which is illustrated in Figure 13.
An internal linear regulator steps down the VPORTP
In order to prevent uncontrolled operations, both
Both VDDH and VDDL regulators turn on as soon as
In non−isolated converter topologies, the high gain
COMP
CS
SS
FB
Blanking
1.2 V
time
Current Slope
Compensation
VDDL
5 mA
11 kW
Soft−start
VDDL
Figure 13. DC−DC Controller Block Diagram
5 kW
10 mA
0
2
1.45 V
360 mV
http://onsemi.com
Current limit
PWM comp
comp
15
Reset
because it is already implemented externally with the shunt
regulator on the secondary side of the DC−DC controller
(see Figure 2). Therefore the FB pin must be strapped to
ARTN and the output transistor of the opto−coupler has to
be connected on the COMP pin where an internal 5 kW
pull−up resistor is tied to the VDDL supply (see Figure 13).
Soft−Start
the output voltage to ramp up in a controlled fashion,
eliminating output voltage overshoot. This function is
programmed by connecting a capacitor Css between the SS
and ARTN pins.
is fully discharged. After coming out of POR, an internal
current source of 5 mA typically starts charging the capacitor
Css to initiate soft−start. When the voltage on SS pin has
reached 0.45 V (typical), the gate driver is enabled and
DC−DC operation starts with a duty cycle limit which
increases with the SS pin voltage. The soft−start function is
finished when the SS pin voltage goes above 1.6 V for which
the duty cycle limit reaches its maximum value of 80
percent.
equation:
CLK
Oscillator
In isolated topologies the error amplifier is not used
The soft−start function provided by the NCP1081 allows
While the DC−DC controller is in POR, the capacitor Css
Soft−start can be programmed by using the following
OSC
CLK
Set
tss(ms) + 0.23
S
R
Q
VPORTP
Gate
Driver
3.3 V LDO
9 V LDO
Css(nf)
VDDL
VDDH
GATE
ARTN