MAX5965AEAX+T Maxim Integrated Products, MAX5965AEAX+T Datasheet - Page 24

• Manufacturer Part Number: MAX5965AEAX+T
• Description: IC PSE CTRLR FOR POE 36SSOP
• Manufacturer: Maxim Integrated Products
• Type: Power Over Ethernet Controller (PoE)r

Specifications of MAX5965AEAX+T

• Applications: IP Phones, Power over LAN, Network Routers and Switches
• Internal Switch(s): No
• Voltage - Supply: 2.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-BSOP (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Power, Quad, Monolithic, PSE Controllers
for Power over Ethernet
Each transmission consists of a START condition (Figure
6) sent by a master, followed by the MAX5965A/
MAX5965B 7-bit slave address plus R/W bit, a register
address byte, one or more data bytes, and finally a
STOP condition.
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master fin-
ishes communicating with the slave, the master issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The STOP condition frees the
bus for another transmission.
Figure 6. START and STOP Conditions
Figure 8. Acknowledge
24
SDAIN
SDA/
SCL
______________________________________________________________________________________
START
S
BY TRANSMITTER
BY RECEIVER
SDA
SDA
SCL
START CONDITION
START and STOP Conditions
S
Serial Addressing
1
STOP
P
2
Each clock pulse transfers one data bit (Figure 7). The
data on SDA must remain stable while SCL is high.
The acknowledge bit is a clocked 9th bit (Figure 8) that
the recipient uses to handshake receipt of each byte of
data. Thus each byte effectively transferred requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA (or the SDAOUT in the 3-wire
interface) during the acknowledge clock pulse, so that
the SDA line is stable low during the high period of the
clock pulse. When the master transmits to the
MAX5965A/MAX5965B, the MAX5965A/MAX5965B
generate the acknowledge bit. When the MAX5965A/
MAX5965B transmit to the master, the master gener-
ates the acknowledge bit.
Figure 7. Bit Transfer
SDA
SCL
CLOCK PULSE FOR ACKNOWLEDGEMENT
DATA LINE STABLE;
DATA VALID
8
DATA ALLOWED
CHANGE OF
9
Acknowledge
Bit Transfer
.