MAX5965AEAX+T Maxim Integrated Products, MAX5965AEAX+T Datasheet - Page 25

• Manufacturer Part Number: MAX5965AEAX+T
• Description: IC PSE CTRLR FOR POE 36SSOP
• Manufacturer: Maxim Integrated Products
• Type: Power Over Ethernet Controller (PoE)r

Specifications of MAX5965AEAX+T

• Applications: IP Phones, Power over LAN, Network Routers and Switches
• Internal Switch(s): No
• Voltage - Supply: 2.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-BSOP (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX5965A/MAX5965B have a 7-bit long slave
address (Figure 9). The bit following the 7-bit slave
address (bit eight) is the R/W bit, which is low for a
write command and high for a read command.
010 always represents the first 3 bits (MSBs) of the
MAX5965A/MAX5965B slave address. Slave address
bits A3, A2, A1, and A0 represent the states of the
MAX5965A/MAX5965B’s A3, A2, A1, and A0 inputs,
allowing up to sixteen MAX5965A/MAX5965B devices
to share the bus. The states of the A3, A2, A1, and A0
latch in upon the reset of the MAX5965A/MAX5965B
into register R11h. The MAX5965A/MAX5965B monitor
the bus continuously, waiting for a START condition fol-
lowed by the MAX5965A/MAX5965B’s slave address.
When a MAX5965A/MAX5965B recognizes its slave
address, the MAX5965A/MAX5965B acknowledge and
are then ready for continued communication.
The global address call is used in writing mode to write
the same register to multiple devices (address 0x60). In
read mode (address 0x61), the global address call is
used as the alert response address. When responding
to a global call, the MAX5965A/MAX5965B put their
own address out on the data line whenever the interrupt
is active. Every other device connected to the SDAOUT
line that has an active interrupt also does this. After
every bit transmitted, the MAX5965A/MAX5965B check
that the data line effectively corresponds to the data it
Figure 9. Slave Address
Figure 10. Control Byte Received
High-Power, Quad, Monolithic, PSE Controllers
Global Addressing and Alert Response Protocol
SDAIN/SDA
SCL
CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION
MSB
0
S
______________________________________________________________________________________
ACKNOWLEDGE FROM THE MAX5965A/MAX5965B
SLAVE ADDRESS
1
Slave Address
0
R/W
0
A3
A
for Power over Ethernet
D15
ACKNOWLEDGE FROM THE MAX5965A/MAX5965B
is delivering. If it is not, it then backs off and frees the
data line. This litigation protocol always allows the part
with the lowest address to complete the transmission.
The microcontroller can then respond to the interrupt
and take proper actions. The MAX5965A/MAX5965B do
not reset their own interrupt at the end of the alert
response protocol. The microcontroller has to do it by
clearing the event register through their CoR adresses
or activating the CLR_INT pushbutton.
A write to the MAX5965A/MAX5965B comprises of the
MAX5965A/MAX5965B’s slave address transmission
with the R/W bit set to 0, followed by at least 1 byte of
information. The first byte of information is the com-
mand byte (Figure 10). The command byte determines
which register of the MAX5965A/MAX5965B is written to
by the next byte, if received. If the MAX5965A/
MAX5965B detect a STOP condition after receiving the
command byte, the MAX5965A/MAX5965B take no fur-
ther action beyond storing the command byte. Any
bytes received after the command byte are data bytes.
The first data byte goes into the internal register of the
MAX5965A/MAX5965B selected by the command byte.
If the MAX5965A/MAX5965B transmit multiple data
bytes before the MAX5965A/MAX5965B detect a STOP
condition, these bytes store in subsequent MAX5965A/
MAX5965B internal registers because the control byte
address autoincrements.
D14
A2
D13
CONTROL BYTE
D12
A1
D11
Message Format for Writing to the
D10
D9
LSB
A0
D8
MAX5965A/MAX5965B
A
R/W
P
ACK
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