MIC2592B-2BTQ Micrel Inc, MIC2592B-2BTQ Datasheet - Page 21

• Manufacturer Part Number: MIC2592B-2BTQ
• Description: IC CTRLR HOTPLUG PCI DUAL 48TQFP
• Manufacturer: Micrel Inc
• Type: Hot-Swap Controllerr

Specifications of MIC2592B-2BTQ

• Applications: General Purpose, PCI Express
• Internal Switch(s): No
• Voltage - Supply: 3.3V, 12V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

inputs are needed for diagnostic purposes, the
/FORCE_ON[A/B] inputs must be enabled; that is, CNTRL[A/B]
Register Bit D[2] should read Logical “0.” Once /FORCE_ON[A/B]
inputs are asserted, all output voltages are present with all
circuit protection features disabled, including overtemperature
protection on VAUX[A/B] outputs. To inhibit /FORCE_ON[A/B]
operation, a Logical “1” shall be written to the CNTRL[A/B]
Register Bit D[2] location(s).
HPI-only Control Applications
In applications where the MIC2592B is controlled only by the
HPI, SMBus signals SCL, SDA, and /INT signals are con-
nected to V
the MIC2592B’s /FAULT[A/B] outputs are activated after
power-on-reset and become asserted when:
Either or both external ON[A/B] and AUXEN[A/B] input signals
are asserted, AND
In order to clear /FAULT[A/B] outputs once asserted, either
or both ON[A/B] and AUXEN[A/B] input signals must be
deasserted. Please see /FAULT[A/B] pin description for ad-
ditional information.
If the /FORCE_ON[A/B] inputs are used for diagnostic pur-
poses, both /FAULT[A/B] and /PWRGD[A/B] outputs are
deasserted once /FORCE_ON[A/B] inputs are asserted.
Serial Port Operation
The MIC2592B uses standard SMBus Write_Byte and
Read_Byte operations for communication with its host. The
SMBus Write_Byte operation involves sending the device’s
target address, with the R/W bit (LSB) set to the low (write)
state, followed by a command byte and a data byte. The SMBus
Read_Byte operation is similar, but is a composite write and
read operation: the host fi rst sends the device’s target address
followed by the command byte, as in a write operation. A new
“Start” bit must then be sent to the MIC2592B, followed by a
MIC2592B Register Set and Programmer’s Model
March 2005
Label
Label
Label
Label
Label
CNTRLA
CNTRLA
CNTRLA
CNTRLA
CNTRLB
CNTRLB
CNTRLB
CNTRLB
STATA
STATA
STATA
STATA
STATB
STATB
STATB
STATB
CS
CS
CS
CS
Reserved
Reserved
Reserved
Reserved
• 12VIN[A/B], 3VIN[A/B], or VSTBY[A/B] input volt-
• The fast OC circuit breaker[A/B] has tripped, OR
• The slow OC circuit breaker[A/B] has tripped AND
• The slow OC circuit breaker[A/B] has tripped AND
• The MIC2592B’s global die temperature > 160°C
age is lower than its respective ULVO threshold,
OR
its fi lter timeout[A/B] has expired, OR
Slot[A/B] die temperature > 140°C, OR
STBY
STBY
STBY
as shown in Figure 6. In this confi guration,
as shown in Figure 6. In this confi guration,
Target Register
Target Register
Target Register
Description
Description
Description
Description
Description
Control Register Slot A
Control Register Slot A
Control Register Slot A
Control Register Slot A
Control Register Slot B
Control Register Slot B
Control Register Slot B
Control Register Slot B
Slot A Status
Slot A Status
Slot A Status
Slot A Status
Slot B Status
Slot B Status
Slot B Status
Slot B Status
Common Status Register
Common Status Register
Common Status Register
Common Status Register
Reserved / Do Not Use
Reserved / Do Not Use
Reserved / Do Not Use
Reserved / Do Not Use
Table 2. MIC2592B Register Addresses
21
repeat of the device address with the R/W bit set to the high
(read) state. The data to be read from the part may then be
clocked out. There is one exception to this rule: If the location
latched in the pointer register from the last write operation is
known to be correct (i.e., points to the desired register within
the MIC2592B), then the “Receive_Byte” procedure may be
used. To perform a Receive_Byte operation, the host sends
an address byte to select the target MIC2592B, with the R/W
bit set to the high (read) state, and then retrieves the data
byte. Figures 10 through 12 show the formats for these data
read and data write procedures.
The Command Register is eight bits (one byte) wide. This
byte carries the address of the MIC2592B’s register to be
operated upon. The command byte values corresponding to
the various MIC2592B register addresses are shown in Table
2. Command byte values other than 0000 0XXX
are reserved and should not be used.
MIC2592B SMBus Address Confi guration
The MIC2592B responds to its own unique SMBus address,
which is assigned using A2, A1, and A0. These represent
the 3 LSBs of its 7-bit address, as shown in Table 3. These
address bits are assigned only during power up of the
VSTBY[A/B] supply input. These address bits allow up to
eight MIC2592B devices in a single system. These pins are
either grounded or left unconnected to specify a logical 0 or
logical 1, respectively. A pin designated as a logical 1 may
also be pulled up to V
A2
A2
A2
A2
A2
07h - FF
07h - FF
07h - FF
07h - FF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
* Where X = "1" for READ and "0" for Write
Read
Read
Read
Read
Read
02
02
02
02
03
03
03
03
04
04
04
04
05
05
05
05
06
06
06
06
Command Byte Value
Command Byte Value
Command Byte Value
h
h
h
h
h
Inputs
Inputs
Table 3. MIC2592B SMBus Addressing
A1
A1
A1
A1
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
h
h
A0
A0
A0
A0
A0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
STBY
STBY
STBY
07h - FF
07h - FF
Write
Write
Write
Write
Write
1000 000X*
1000 000X*
1000 000X*
1000 000X*
.
.
02
02
03
03
04
04
05
05
06
06
MIC2592B Device Address
MIC2592B Device Address
1000 001X
1000 001X
1000 001X
1000 001X
1000 010X
1000 010X
1000 010X
1000 010X
1000 011X
1000 011X
1000 011X
1000 011X
1000 100X
1000 100X
1000 100X
1000 100X
1000 101X
1000 101X
1000 101X
1000 101X
1000 110X
1000 110X
1000 110X
1000 110X
1000 111X
1000 111X
1000 111X
1000 111X
h
h
h
h
h
Binary
Binary
Binary
Binary
Binary
h
h
b
b
b
b
b
b
b
b
xxxx 0000
xxxx 0000
Power-On
Power-On
Power-On
Undefi ned
Undefi ned
Default
Default
Default
Default
b
00
00
00
00
00
00
00
00
M9999-033105
= 00
Hex
Hex
Hex
Hex
Hex
h
h
h
h
8A
8A
8C
8C
8E
8E
80
80
82
82
84
84
86
86
88
88
h
h
h
h
h
h
h
h
h
b
– 07
h