MIC2592B-2BTQ Micrel Inc, MIC2592B-2BTQ Datasheet - Page 24

IC CTRLR HOTPLUG PCI DUAL 48TQFP

MIC2592B-2BTQ

Manufacturer Part Number
MIC2592B-2BTQ
Description
IC CTRLR HOTPLUG PCI DUAL 48TQFP
Manufacturer
Micrel Inc
Type
Hot-Swap Controllerr
Datasheet

Specifications of MIC2592B-2BTQ

Applications
General Purpose, PCI Express
Internal Switch(s)
No
Voltage - Supply
3.3V, 12V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MIC2592B-2BTQ
Manufacturer:
Micrel Inc
Quantity:
10 000
Part Number:
MIC2592B-2BTQ TR
Manufacturer:
Micrel Inc
Quantity:
10 000
Status Register Slot A (STATA)
8-Bits, Read-Only
The power-up default value is 00h. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to an
overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert /INT. The
status of the /FAULTA pin is not affected by reading the Status Register or by clearing active status bits.
Notes:
2.
March 2005
1.
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
VAUXAF
VAUXAF
VAUXAF
VAUXAF
FAULTA
FAULTA
FAULTA
FAULTA
FAULTA
FAULTA
FAULTA
FAULTA
FAULTA
FAULTA
FAULTA
FAULTA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
MAINA
MAINA
MAINA
MAINA
MAINA
12VAF
12VAF
12VAF
12VAF
If FAULTA has been set by an overcurrent condition on one or more of the MAIN outputs, the ONA input must go LOW to reset FAULTA.
If FAULTA has been set by a VAUXA overcurrent event, the AUXENA input must go LOW to reset FAULTA.
If an overcurrent has occurred on both a MAIN output and the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset
FAULTA.
Neither the FAULTA bits nor the /FAULTA pins are active when the MIC2592B power paths are controlled by the System Management Interface.
When using SMI power path control, AUXENA and ONA pins for that slot must be tied to GND.
Bit(s)
Bit(s)
Bit(s)
3VAF
3VAF
3VAF
D[7]
D[7]
D[7]
D[7]
D[7]
D[7]
D[7]
D[7]
D[3]
D[3]
D[3]
D[3]
D[1]
D[1]
D[1]
Power-Up Default Value:
Command_Byte Value (R/W):
FAULT Status - Slot A
FAULT Status - Slot A
FAULT Status - Slot A
FAULT Status - Slot A
MAIN Enable Status - Slot A
MAIN Enable Status - Slot A
MAIN Enable Status - Slot A
MAIN Enable Status - Slot A
MAIN Enable Status - Slot A
VAUX Enable Status - Slot A
VAUX Enable Status - Slot A
VAUX Enable Status - Slot A
VAUX Enable Status - Slot A
VAUX Enable Status - Slot A
Overcurrent Fault: VAUXA supply
Overcurrent Fault: VAUXA supply
Overcurrent Fault: VAUXA supply
Overcurrent Fault: VAUXA supply
Reserved
Reserved
Reserved
Reserved
Overcurrent Fault: +12V supply
Overcurrent Fault: +12V supply
Overcurrent Fault: +12V supply
Overcurrent Fault: +12V supply
Reserved
Reserved
Reserved
Overcurrent Fault: 3.3V supply
Overcurrent Fault: 3.3V supply
Overcurrent Fault: 3.3V supply
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
MAINA
MAINA
MAINA
MAINA
MAINA
MAINA
MAINA
MAINA
D[6]
D[6]
D[6]
D[6]
D[6]
D[6]
D[6]
D[6]
two Main Power outputs for Slot A
two Main Power outputs for Slot A
two Main Power outputs for Slot A
Auxiliary Power output for Slot A
Auxiliary Power output for Slot A
Auxiliary Power output for Slot A
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
Function
Function
Function
D[5]
D[5]
D[5]
D[5]
D[5]
D[5]
D[5]
D[5]
Status Register, Slot A (STATA)
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
VAUXAF
VAUXAF
VAUXAF
VAUXAF
VAUXAF
VAUXAF
VAUXAF
VAUXAF
D[4]
D[4]
D[4]
D[4]
D[4]
D[4]
D[4]
D[4]
0000 0000b = 00h
0000 0100b = 04h
24
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
D[3]
D[3]
D[3]
D[3]
D[3]
D[3]
D[3]
D[3]
1 = Fault pin asserted
1 = Fault pin asserted
1 = Fault pin asserted
1 = Fault pin asserted
(/FAULTA pin is LOW)
(/FAULTA pin is LOW)
(/FAULTA pin is LOW)
(/FAULTA pin is LOW)
0 = Fault pin deasserted
0 = Fault pin deasserted
0 = Fault pin deasserted
0 = Fault pin deasserted
(/FAULTA pin is HIGH)
(/FAULTA pin is HIGH)
(/FAULTA pin is HIGH)
(/FAULTA pin is HIGH)
See Notes 1, 2, and 3.
See Notes 1, 2, and 3.
See Notes 1, 2, and 3.
See Notes 1, 2, and 3.
Represents the actual state (on/off) of the
Represents the actual state (on/off) of the
Represents the actual state (on/off) of the
Represents the actual state (on/off) of the
Represents the actual state (on/off) of the
(+12V and +3.3V)
(+12V and +3.3V)
(+12V and +3.3V)
(+12V and +3.3V)
1 = Main Power ON
1 = Main Power ON
1 = Main Power ON
1 = Main Power ON
0 = Main Power OFF
0 = Main Power OFF
0 = Main Power OFF
0 = Main Power OFF
Represents the actual state (on/off) of the
Represents the actual state (on/off) of the
Represents the actual state (on/off) of the
Represents the actual state (on/off) of the
Represents the actual state (on/off) of the
1 = AUX Power ON
1 = AUX Power ON
1 = AUX Power ON
1 = AUX Power ON
0 = AUX Power OFF
0 = AUX Power OFF
0 = AUX Power OFF
0 = AUX Power OFF
1 = Fault 0 = No fault
1 = Fault 0 = No fault
1 = Fault 0 = No fault
1 = Fault 0 = No fault
Always read as zero
Always read as zero
Always read as zero
Always read as zero
1 = Fault 0 = No fault
1 = Fault 0 = No fault
1 = Fault 0 = No fault
1 = Fault 0 = No fault
Always read as zero
Always read as zero
Always read as zero
1 = Fault 0 = No fault
1 = Fault 0 = No fault
1 = Fault 0 = No fault
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
12VAF
12VAF
12VAF
12VAF
12VAF
12VAF
12VAF
12VAF
D[2]
D[2]
D[2]
D[2]
D[2]
D[2]
D[2]
D[2]
Operation
Operation
Operation
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
D[1]
D[1]
D[1]
D[1]
D[1]
D[1]
D[1]
D[1]
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
M9999-033105
3VAF
3VAF
3VAF
3VAF
3VAF
3VAF
3VAF
3VAF
D[0]
D[0]
D[0]
D[0]
D[0]
D[0]
D[0]
D[0]

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