MIC2592B-2BTQ Micrel Inc, MIC2592B-2BTQ Datasheet - Page 5

• Manufacturer Part Number: MIC2592B-2BTQ
• Description: IC CTRLR HOTPLUG PCI DUAL 48TQFP
• Manufacturer: Micrel Inc
• Type: Hot-Swap Controllerr

Specifications of MIC2592B-2BTQ

• Applications: General Purpose, PCI Express
• Internal Switch(s): No
• Voltage - Supply: 3.3V, 12V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Description (continued)
March 2005
Pin Number
Pin Number
Pin Number
Pin Number
35
35
35
35
31
31
31
31
26
26
26
26
15
15
15
15
22
22
22
22
44
44
44
44
43
43
43
43
45
45
45
45
42
42
42
42
36
36
36
36
28
28
28
28
38
38
38
11
11
11
2
2
2
2
6
6
6
1
1
1
1
9
9
9
9
4
4
4
4
/FORCE_ONA
/FORCE_ONA
/FORCE_ONA
/FORCE_ONA
/FORCE_ONB
/FORCE_ONB
/FORCE_ONB
/FORCE_ONB
CFILTERA
CFILTERA
CFILTERA
CFILTERA
CFILTERB
CFILTERB
CFILTERB
CFILTERB
/PWRGDA
/PWRGDA
/PWRGDA
/PWRGDB
/PWRGDB
/PWRGDB
/PWRGDB
Pin Name
Pin Name
Pin Name
Pin Name
AUXENA
AUXENA
AUXENA
AUXENA
AUXENB
AUXENB
AUXENB
AUXENB
VSTBYB
VSTBYB
VSTBYB
VSTBYB
/FAULTB
/FAULTB
/FAULTB
/FAULTB
VSTBYA
VSTBYA
VSTBYA
/FAULTA
/FAULTA
/FAULTA
/FAULTA
GPI_A0
GPI_A0
GPI_A0
GPI_A0
GPI_B0
GPI_B0
GPI_B0
VAUXA
VAUXA
VAUXA
VAUXA
VAUXB
VAUXB
VAUXB
VAUXB
ONB
ONB
ONB
ONB
ONA
ONA
ONA
ONA
Pin Function
Pin Function
Pin Function
Pin Function
Overcurrent Timers: Capacitors connected between these
Overcurrent Timers: Capacitors connected between these
Overcurrent Timers: Capacitors connected between these
Overcurrent Timers: Capacitors connected between these
pins and GND set the duration of t
pins and GND set the duration of t
pins and GND set the duration of t
pins and GND set the duration of t
delay (t
delay (t
delay (t
delay (t
before its circuit breaker is tripped.
before its circuit breaker is tripped.
before its circuit breaker is tripped.
before its circuit breaker is tripped.
/PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has
/PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has
/PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has
been commanded to turn on and has successfully begun delivering power to
been commanded to turn on and has successfully begun delivering power to
been commanded to turn on and has successfully begun delivering power to
been commanded to turn on and has successfully begun delivering power to
its respective +12V, +3.3V, and VAUX outputs. Each pin requires an external
its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern
its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern
its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern
pull-up resistor to V
pull-up resistor to V
pull-up resistor to V
pull-up resistor to V
3.3V Standby Input Voltage: Required to support PCI Express VAUX output.
3.3V Standby Input Voltage: Required to support PCI Express VAUX output.
3.3V Standby Input Voltage: Required to support PCI Express VAUX output.
Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
to ensure that the chip is accessible during standby modes. A UVLO circuit
to ensure that the chip is accessible during standby modes. A UVLO circuit
to ensure that the chip is accessible during standby modes. A UVLO circuit
to ensure that the chip is accessible during standby modes. A UVLO circuit
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
threshold. Both pins must be externally connected together at the MIC2592B
threshold. Both pins must be externally connected together at the MIC2592B
threshold. Both pins must be externally connected together at the MIC2592B
threshold. Both pins must be externally connected together at the MIC2592B
controller.
controller.
controller.
controller.
3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect
3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect
3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect
3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect
the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
400mΩ MOSFETs. These outputs are current limited and protected against
400mΩ MOSFETs. These outputs are current limited and protected against
400mΩ MOSFETs. These outputs are current limited and protected against
400mΩ MOSFETs. These outputs are current limited and protected against
short-circuit faults.
short-circuit faults.
short-circuit faults.
short-circuit faults.
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
these controls only after the V
these controls only after the V
these controls only after the V
these controls only after the V
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
these pins to GND if using SMI power control. Also, see pin description for
these pins to GND if using SMI power control. Also, see pin description for
these pins to GND if using SMI power control. Also, see pin description for
these pins to GND if using SMI power control. Also, see pin description for
/FAULTA and /FAULTB.
/FAULTA and /FAULTB.
/FAULTA and /FAULTB.
/FAULTA and /FAULTB.
Enable Inputs: Rising-edge triggered. Used to enable or disable the
Enable Inputs: Rising-edge triggered. Used to enable or disable the
Enable Inputs: Rising-edge triggered. Used to enable or disable the
Enable Inputs: Rising-edge triggered. Used to enable or disable the
VAUX[A/B] outputs. The outputs can be switched on by these controls only
VAUX[A/B] outputs. The outputs can be switched on by these controls only
VAUX[A/B] outputs. The outputs can be switched on by these controls only
VAUX[A/B] outputs. The outputs can be switched on by these controls only
after the V
after the V
after the V
after the V
Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets
Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets
Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets
Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
SMI power control. Also, see pin description for /FAULTA and /FAULTB.
SMI power
SMI power
SMI power
/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the
/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the
/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the
/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the
circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to V
overtemperature). Each pin requires an external pull-up resistor to V
overtemperature). Each pin requires an external pull-up resistor to V
overtemperature). Each pin requires an external pull-up resistor to V
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
was asserted in response to a fault condition on one of the slot’s MAIN out-
was asserted in response to a fault condition on one of the slot’s MAIN out-
was asserted in response to a fault condition on one of the slot’s MAIN out-
was asserted in response to a fault condition on one of the slot’s MAIN out-
puts (+12V or +3.3V).
puts (+12V or +3.3V).
puts (+12V or +3.3V).
puts (+12V or +3.3V).
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] was asserted in response to a fault condition on the slot’s
/FAULT[A/B] was asserted in response to a fault condition on the slot’s
/FAULT[A/B] was asserted in response to a fault condition on the slot’s
/FAULT[A/B] was asserted in response to a fault condition on the slot’s
VAUX output. If a fault condition occurred on both the MAIN and VAUX
VAUX output. If a fault condition occurred on both the MAIN and VAUX
VAUX output. If a fault condition occurred on both the MAIN and VAUX
VAUX output. If a fault condition occurred on both the MAIN and VAUX
outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be
outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be
outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be
outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be
brought low to deassert the /FAULT[A/B] output.
brought low to deassert the /FAULT[A/B] output.
brought low to deassert the /FAULT[A/B] output.
brought low to deassert the /FAULT[A/B] output.
Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
VAUX), while specifi cally defeating all protections on those supplies. This
VAUX), while specifi cally defeating all protections on those supplies. This
VAUX), while specifi cally defeating all protections on those supplies. This
VAUX), while specifi cally defeating all protections on those supplies. This
explcitly includes all overcurrent and short circuit protections, and on-chip
explcitly includes all overcurrent and short circuit protections, and on-chip
explcitly includes all overcurrent and short circuit protections, and on-chip
explcitly includes all overcurrent and short circuit protections, and on-chip
thermal protection for the VAUX[A/B] supplies. Additionally included are the
UVLO protections for the +3.3V and +12V main supplies. The
UVLO protections for the +3.3V and +12V main supplies. The
UVLO protections for the +3.3V and +12V main supplies. The
UVLO protections for the +3.3V and +12V main supplies. The
/FORCE_ON[A/B] pins do not disable UVLO protection for the VAUX[A/B]
/FORCE_ON[A/B] pins do
/FORCE_ON[A/B] pins do
/FORCE_ON[A/B] pins do
supplies. These input pins are intended for diagnostic purposes only.
supplies. These input pins are intended for diagnostic purposes only.
supplies. These input pins are intended for diagnostic purposes only.
supplies. These input pins are intended for diagnostic purposes only.
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
register set will continue to refl ect the actual state of each slot’s supplies.
register set will continue to refl ect the actual state of each slot’s supplies.
register set will continue to refl ect the actual state of each slot’s supplies.
register set will continue to refl ect the actual state of each slot’s supplies.
There is a pair of register bits, accessible via the SMBus, which can be set
There is a pair of register bits, accessible via the SMBus, which can be set
There is a pair of register bits, accessible via the SMBus, which can be set
There is a pair of register bits, accessible via the SMBus, which can be set
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
pins -- See CNTRL[A/B] Register Bit D[2].
pins -- See CNTRL[A/B] Register Bit D[2].
pins -- See CNTRL[A/B] Register Bit D[2].
pins -- See CNTRL[A/B] Register Bit D[2].
General Purpose Inputs: The states of these two inputs are available by
General Purpose Inputs: The states of these two inputs are available by
General Purpose Inputs: The states of these two inputs are available by
General Purpose Inputs: The states of these two inputs are available by
reading the Common Status Register, Bits [4:5]. If not used, connect each
reading the Common Status Register, Bits [4:5]. If not used, connect each
reading the Common Status Register, Bits [4:5]. If not used, connect each
pin to GND.
pin to GND.
pin to GND.
pin to GND.
FLT
) is the amount of time for which a slot remains in current limit
STBY
STBY
STBY
5
input supply is valid and stabe (i.e., t
input supply is valid and stabe (i.e., t
STBY
STBY
STBY
.
.
STBY
STBY
STBY
FLT
input supply is valid and stabe (i.e., t
input supply is valid and stabe (i.e., t
for each slot. The overcurrent fi lter
POR
elapses - See the
M9999-033105
STBY
STBY
STBY
POR
.
.