ISL6420AIAZ-TK Intersil, ISL6420AIAZ-TK Datasheet - Page 16

• Manufacturer Part Number: ISL6420AIAZ-TK
• Description: IC CTRLR PWM SYNC BUCK 20-QSOP
• Manufacturer: Intersil

Specifications of ISL6420AIAZ-TK

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.4MHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 28 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QSOP
• Frequency-max: 1.4MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL6420AIAZ-TKTR

Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6420A) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180°. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 16. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
Figure 17 shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 17. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 17 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
F
F
F
F
F
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
LC
ESR
Z1
P1
Z2
P2
(~75% F
=
=
=
=
=
FB
=
-------------------------------------- -
2π
----------------------------------
2π R3 C3
----------------------------------
2π R
------------------------------------------------------ -
2π R2
----------------------------------------------------- -
2π
-------------------------------------------- -
2π
. The goal of the compensation network is to provide
•
•
•
•
•
•
ST
ND
ST
ND
(
0dB
1
L
(
R1
1
1
LC
2 C1
ESR C
O
•
•
Zero Below Filter’s Double Pole
Pole at the ESR Zero
•
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
1
)
•
) and adequate phase margin. Phase margin
+
1
1


C
--------------------- -
C1
R3
C1 C2
•
O
) C3
+
•
O
•
C2
)


16
0dB
(EQ. 4)
(EQ. 5)
(EQ. 6)
(EQ. 7)
(EQ. 8)
(EQ. 9)
P2
and
IN
ISL6420A
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1.0µF
ceramic capacitors in the 1206 surface-mount package.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors.
The bulk capacitor’s ESR will determine the output ripple
voltage and the initial voltage drop after a high slew-rate
transient. An aluminum electrolytic capacitor's ESR value is
related to the case size with lower ESR available in larger
FIGURE 17. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
100
-20
-40
-60
80
60
40
20
0
and Z
10
(R2/R1)
20LOG
IN
MODULATOR
to provide a stable, high bandwidth (BW) overall
100
GAIN
1K
F
Z1
F
FREQUENCY (Hz)
LC
F
Z2
10K
F
P1
F
(V
ESR
100K
IN
20LOG
F
/
∆
P2
V
OSC
OPEN LOOP
ERROR AMP GAIN
1M
)
COMPENSATION
GAIN
CLOSED LOOP
GAIN
October 13, 2005
10M
FN9169.1