ADP3208DJCPZ-RL ON Semiconductor, ADP3208DJCPZ-RL Datasheet - Page 6

• Manufacturer Part Number: ADP3208DJCPZ-RL
• Description: IC CTLR BUCK 7BIT 2PHASE 48LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3208DJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.01 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Output Voltage: 10 mV
• Output Current: 40 A
• Input Voltage: 19 V
• Supply Current: 6 mA
• Switching Frequency: 300 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 10 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS
= PGND2 = Low = 0 V, EN = VATFREQ = High, DPRSLP = 0 V, PSI = 1.05 V, V
noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. R
VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP)
VID DAC VOLTAGE REFERENCE
VOLTAGE MONITORING AND PROTECTION − Power Good
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Timing is referenced to the 90% and 10% points, unless otherwise noted.
FB, LLINE Voltage Range
(Note 2)
FB, LLINE Offset Voltage
(Note 2)
FB LLINE Bias Current
(Note 2)
LLINE Positioning Accuracy
COMP Voltage Range
COMP Current
COMP Slew Rate
Gain Bandwidth (Note 2)
V
V
V
V
V
Soft−Start Delay (Note 2)
Soft−Start Time
Boot Delay
V
FBRTN Current
CSREF Undervoltage
Threshold
CSREF Overvoltage
Threshold
CSREF Crowbar Voltage
Threshold
CSREF Reverse Voltage
Threshold
DAC
DAC
DAC
DAC
DAC
DAC
Voltage Range (Note 3)
Accuracy
Differential Non−linearity (Note 2)
Line Regulation
Boot Voltage (Note 2)
Slew Rate
Parameter
V
V
V
V
V
V
V
V
FB
SR
Symbol
V
FB
FB
UVCSREF
OVCSREF
CBCSREF
RVCSREF
V
I
I
BOOTFB
t
GBW
DV
FBRTN
OSVEA
COMP
t
BOOT
, V
COMP
I
DSS
t
COMP
− V
− V
FB
SS
FB
LLINE
V
VID
VID
CC
= P
VCC1
Relative to CSREF = V
Relative to CSREF = V
Measured on FB relative to V
forced 80 mV below CSREF
Operating Range
COMP = 2.0 V, CSREF = V
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
C
Open loop configuration
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
Non−inverting unit gain configuration,
R
See VID Code Table
Measured on FB (includes offset),
relative to V
V
V
V
Measured during boot delay period
Measured from EN pos edge to FB = 50 mV
Measured from EN pos edge to FB settles to
V
Measured from FB settling to V
within −5% to CLKEN neg edge
Soft−Start
Non−LSB VID step, DPRSLP = H,
Slow C4 Entry/Exit
Non−LSB VID step, DPRSLP = L,
Fast C4 Exit
Relative to DAC Voltage:
Relative to nominal DAC Voltage
Relative to FBRTN
Relative to FBRTN, Latchoff mode:
COMP
FB
VID
VID
CC
BOOT
CSREF Falling
CSREF Rising
= P
= 1 kW
= 4.75 V to 5.25 V
= 1.2125 V to 1.5000 V
= 0.3000 V to 1.2000 V
http://onsemi.com
= 1.2 V within −5%
VCC2
= 10 pF, CSREF = V
VID
= BST1 = BST2 = High = 5.0V, FBRTN = GND = SW1 = SW2 = PGND1
, for VID table see Table 3,
6
Conditions
DAC
DAC
= 0.5 V to 1.5 V
= 0.3 V to 0.4875 V
VID
REF
DAC
DAC
VID
= 1.2000 V, T
BOOT
= 80 kW.
,
, LLINE
= 1.2 V
A
= −40°C to 100°C, unless otherwise
−200
−100
−360
−360
−350
−0.5
0.85
−9.0
−7.5
−1.0
1.57
Min
−78
150
0
0.0625
−0.75
1.200
−300
−300
−300
0.05
0.25
Typ
−80
−20
200
150
200
−70
6.0
1.7
1.0
1.7
15
20
90
+200
−240
−160
Max
+0.5
+9.0
+7.5
+1.0
1.78
−5.0
100
−82
200
250
4.0
1.5
LSB/ms
MHz
Unit
V/ms
LSB
mV
mV
mV
mA
mV
mV
mV
mV
ms
mA
ms
ms
%
A
V
V
V
V