NCP5318FTR2G ON Semiconductor, NCP5318FTR2G Datasheet - Page 17

• Manufacturer Part Number: NCP5318FTR2G
• Description: IC CTLR CPU 2/3/4 PHASE 32-LQFP
• Manufacturer: ON Semiconductor

Specifications of NCP5318FTR2G

• Applications: Controller, CPU
• Voltage - Input: 9.5 ~ 13.2 V
• Number Of Outputs: 4
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Switching Frequency: 1 MHz
• Mounting Style: SMD/SMT
• Primary Input Voltage: 18V
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD
• Supply Voltage Min: 12V
• Packaging Type: Tape And Reel
• Peak Reflow Compatible (260 C): Yes
• Frequency: 1MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP5318FTR2G; NCP5318FTR2GOSTR

efficiency at 100 A full load, the Error Amplifier output
changes by:
voltage change resulting from the synthesized, closed loop
output impedance (referred to as the output loadline) is as
follows:
Summation of this change at the PWM comparator input
forces the Error Amplifier output voltage to respond with an
identical change which always opposes that forced by the
DV COMP + 1.0 mW
For the converter described above with 4 phases and 85%
Additionally, if the “Droop” feature is used, the output
where R
+ 83 mV
LL
(25 mV ) 3.0 V V
is the value, in ohms, of the output loadline.
Internal Ramp
DV + * R LL
V
FFB
SWNODE
CSA Out
(V
COMP
3.0 V
OUT
V
2
)
100 A
DI OUT
14.8 mV)
4
CSA Output +
Internal Ramp +
Offset + CSxN
)
Figure 18. Open Loop Operation
(1 * 0.85)
0.85
http://onsemi.com
T1
17
sensed current previously described, which reduces the
amount of Error Amplifier output movement required.
comparator and resulting phase current upon an output
voltage dip. Before T1, the converter is in steady−state
operation. The inductor current provides a portion of the
PWM ramp through the current sense amplifier. The PWM
cycle ends when the sum of the current ramp, the “partial”
internal ramp, the offset and the output voltage exceeds the
level of the COMP pin. At T1, the load current increases and
the output voltage sags. The next PWM cycle begins and the
cycle continues longer than before until T2, when the current
signal has increased enough to make up for the lower voltage
at the VFB pin. After T2, the output voltage remains lower,
and the average current signal level (CSA output) is raised
so that the sum of the current and voltage signal is the same
as with the original load. In a closed loop system, the COMP
pin would move higher to restore the output voltage to the
original level.
Figure 18 shows the open loop response of the PWM
T2