NCP5318FTR2G ON Semiconductor, NCP5318FTR2G Datasheet - Page 20

• Manufacturer Part Number: NCP5318FTR2G
• Description: IC CTLR CPU 2/3/4 PHASE 32-LQFP
• Manufacturer: ON Semiconductor

Specifications of NCP5318FTR2G

• Applications: Controller, CPU
• Voltage - Input: 9.5 ~ 13.2 V
• Number Of Outputs: 4
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Switching Frequency: 1 MHz
• Mounting Style: SMD/SMT
• Primary Input Voltage: 18V
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD
• Supply Voltage Min: 12V
• Packaging Type: Tape And Reel
• Peak Reflow Compatible (260 C): Yes
• Frequency: 1MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP5318FTR2G; NCP5318FTR2GOSTR

signal from being asserted for 2 ms (typically) from the time
that VOUT goes into range. If VOUT goes out of range,
PWRGD will be deasserted immediately (typically less than
2 ms).
comparator is externally programmable by adjusting
resistors R1 and R2 shown in Figure 22. The following
equations can be used to calculate the upper and lower
threshold voltages:
Undervoltage Lockout
This circuit keeps the IC’s output drivers low until V
applied to the IC reaches 9.0 V. The GATE outputs are
disabled when V
Soft−Start
The total SS capacitance will begin to charge with a current
of 70 mA. The error amplifier directly charges the COMP
capacitance. An internal clamp ensures that the COMP pin
voltage will always be less than the voltage at the SS pin,
ensuring proper startup behavior. All GATE outputs are held
low until the COMP voltage reaches 0.6 V. Once this
threshold is reached, the GATE outputs are released to
operate normally.
Current Limit
total current signal to a user adjustable voltage on the I
pin. If the I
the converter is latched off. V
latch.
Fault Protection Logic
prevent harmful modes of operation from occurring. The
fault logic is described in Table 1.
Table 1. DESCRIPTION OF FAULT LOGIC
Overvoltage Lockout
Enable Low
Module Overcurrent Limit
DAC Code = 11111x
V
PWRLS Out of Range
An internal timer in the NCP5318 prevents the PWRGD
The lower voltage threshold of the Power Good
The NCP5318 includes an undervoltage lockout circuit.
At initial power−up, both SS and COMP voltages are zero.
The individual phase currents are summed to compare a
The NCP5318 includes fault protection circuitry to
REF
V LOWER +
V UPPER + V OUTNoLoad ) 100 mV
Undervoltage Lockout
LIM
Faults
voltage is exceeded, the fault latch trips and
CC
V OUTNoLoad
drops below 8.0 V.
2
CC
must be recycled to reset the
Stop Switching
R 1 ) R 2
Yes
Yes
Yes
Yes
Yes
No
R 2
Depends on output voltage level
Depends on output voltage level
Depends on output voltage level
Depends on output voltage level
http://onsemi.com
LIM
CC
PWRGD Level
De−asserted
20
Gate Outputs
drivers. Accordingly, the gate outputs are capable of driving
a 100 pF load with typical rise and fall times of 5.0 ns.
the Gate Outputs. The DRVON signal is intended to be used
as an enable signal for external gate drivers, such as the
NCP3418B. If the DRVON signal is low, the gate driver will
be disabled and both MOSFETs in the synchronous rectified
phase channel will be held in the off position. If the DRVON
signal is high, the gate driver will be enabled. The high side
MOSFET will be enabled if the Gate Output is high and
DRVON is high. The low side MOSFET will be enabled if
the Gate Output is low and DRVON is high. The DRVON
signal at power up will initially go high as V
the power on reset (POR) of the IC, roughly 5 V. It will stay
high until the V
the part. DRVON will then go to a low state and stay low
until the part is enabled or an OVP is detected.
Digital to Analog Converter (DAC)
6−bit, 0.5% DAC. The VID pins must be pulled high
externally. A 1.0 kW pullup to a maximum of 3.3 V is
recommended to meet Intel specifications. To ensure valid
logic signals, the designer should ensure at least 800 mV will
be present at the IC for a logic high. The output of the DAC
is described in the Electrical Characteristics section of the
data sheet. These outputs are consistent with VR 10.x and
processor specifications. The DAC output is equal to the
VID code specification minus 19 mV. The latest VR and
processor specifications require a power supply to turn its
output off in the event of a 11111X VID code. When the
DAC sees such a code, the GATE pins stop switching and go
low. This condition is described in Table 1.
The NCP5318 is designed to operate with external gate
An additional signal, DRVON, works in conjunction with
The output voltage of the NCP5318 is set by means of a
Results
CC
Enable
Driver
High
High
Low
Low
Low
Low
voltage exceeds the UVLO threshold of
SS Character-
Not Affected
−0.3 mA
−0.3 mA
−0.3 mA
−0.3 mA
−0.3 mA
istics
Change VID Code
Reset Method
Not Affected
Not Affected
CC
Power On
Power On
Power On
rises above