NB7L14MMNEVB ON Semiconductor, NB7L14MMNEVB Datasheet - Page 8

EVAL BOARD FOR NB7L14MMN

NB7L14MMNEVB

Manufacturer Part Number
NB7L14MMNEVB
Description
EVAL BOARD FOR NB7L14MMN
Manufacturer
ON Semiconductor
Datasheet

Specifications of NB7L14MMNEVB

Main Purpose
Timing, Clock Buffer / Driver / Receiver / Translator
Embedded
No
Utilized Ic / Part
NB7L14M
Primary Attributes
Input Up To 12Gb/s & 8GHz
Secondary Attributes
Differential CML Output
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
NB7L14MMNEVBOS
Table 6. INTERFACING OPTIONS
INTERFACING OPTIONS
RSECL, LVPECL
LVTTL, LVCMOS
AC−COUPLED
LVDS
CML
An external voltage should be applied to the unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and V
Bias V
Standard ECL Termination Techniques. See AND8020/D.
50 W
TCLK
Figure 14. CML Output Structure
Connect V
, V
TCLK
Connect V
http://onsemi.com
Inputs within (VCMR) Common Mode Range
TCLK
V
V
CC
EE
CONNECTIONS
, V
TCLK
8
TCLK
16 mA
and V
Together for CLK Input
TCLK
50 W
CC
to V
/2 for LVCMOS inputs.
CC
Q
Q

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