CDB4270 Cirrus Logic Inc, CDB4270 Datasheet - Page 12

BOARD EVAL FOR CS4270 CODEC

CDB4270

Manufacturer Part Number
CDB4270
Description
BOARD EVAL FOR CS4270 CODEC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CDB4270

Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS4270
Primary Attributes
Stereo, 24-Bit, 192 kHz Sample Rate
Secondary Attributes
I²S, S/PDIF Inputs and Outputs, Analog Inputs and Outputs, GUI
Description/function
Audio CODECs
Operating Supply Voltage
5 V
Product
Audio Modules
For Use With/related Products
CS4270
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1002
12
2.5
.
OSC
External MCLK Control
Several sources for MCLK exist on the CDB4270. The crystal oscillator, Y1, will master the MCLK bus when
no S/PDIF signal is input to the CS8416 (refer to the CS8416 data sheet for details on OMCK operation).
When S/PDIF data is present at the CS8416 input, the CS8416 generates a master clock whenever its in-
ternal PLL is locked to the incoming S/PDIF stream.
The DSP Header can master the MCLK bus or be an observation point for MCLK depending upon the state
of the driver control signals from the FPGA.
Refer to the Register Description section of this document for a description of the MCLK routing control reg-
isters.
OMCK
DSP Header
CS8416
CS8406
OMCK
RMCK
MCLK
Figure 6. External MCLK Control
MCLK.FROM.8416
MCLK.TO.HDR
MCLK.FROM.HDR
MCLK
FPGA
MCLK
CS4270
CDB4270
DS686DB3

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