CDB4270 Cirrus Logic Inc, CDB4270 Datasheet - Page 18

BOARD EVAL FOR CS4270 CODEC

CDB4270

Manufacturer Part Number
CDB4270
Description
BOARD EVAL FOR CS4270 CODEC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CDB4270

Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS4270
Primary Attributes
Stereo, 24-Bit, 192 kHz Sample Rate
Secondary Attributes
I²S, S/PDIF Inputs and Outputs, Analog Inputs and Outputs, GUI
Description/function
Audio CODECs
Operating Supply Voltage
5 V
Product
Audio Modules
For Use With/related Products
CS4270
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1002
18
4. HARDWARE MODE
When the Flex GUI is not running on a PC or when the USB or serial port cables are not connected to the CDB4270
from the PC, the board is automatically in Hardware Control Mode. When in this control mode, dip switches S1 and
S2 control the board’s functionality. Note: Hardware Mode controls are a subset of Software Mode controls, and
some FPGA or CS4270 register bits cannot be changed in Hardware Mode. See
tings” on page 24
5. FPGA GUI REGISTER DESCRIPTION
As mentioned previously, the CS4270 and FPGA registers are directly accessible in Software Mode within the Flex
GUI. In Hardware Mode, the FPGA registers control all board functions. The FPGA register descriptions for both
modes are described below. For a description of the CS4270 registers, see the CS4270 data sheet.
5.1
Addr
00h
01h
02h
03h
Code Rev. ID
SDIO/CLK/SW/HW
Control
CS8406 Control
CS8416 Control
FPGA REGISTER QUICK REFERENCE
The table below shows the register names and their associated default values.
Note:
Function
Default “power on” bit states are shown.
of this document for a complete description of the Hardware Mode settings.
Reserved
TXCLK.1
SDIO.1
REV.7
7
0
0
0
0
TXCLK.0
RXCLK
SDIO.0
REV.6
6
0
0
0
0
Reserved
Reserved
Reserved
REV.5
5
0
0
0
0
RX_M/S
TX_M/S
REV.4
MCLK
4
1
1
0
0
DUT_SDIO.1
TX_FMT
RX_FMT
REV.3
3
0
0
0
0
DUT_SDIO.0
Reserved
Reserved
REV.2
“CDB4270 Hardware Mode Set-
2
1
0
0
0
SUB_CK.1
TXSDIO.1
Reserved
REV.1
1
1
0
0
0
CDB4270
DS686DB3
SUB_CK.0
TXSDIO.0
Reserved
REV.0
0
1
0
1
0

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