SI5324-EVB Silicon Laboratories Inc, SI5324-EVB Datasheet - Page 21

• Manufacturer Part Number: SI5324-EVB
• Description: BOARD EVALUATION SI5324
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5324-EVB

• Main Purpose: Timing, Clock Multiplier
• Embedded: No
• Utilized Ic / Part: SI5324
• Primary Attributes: 2 Inputs, 2 Outputs
• Secondary Attributes: CML, CMOS, LVDS, LVPECL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Reset value = 0000 0101
Register 3.
Name
Type
7:6
3:0
Bit
Bit
5
4
CKSEL_REG
SQ_ICAL
Reserved
DHOLD
CKSEL_REG [1:0]
Name
D7
[1:0]
R/W
CKSEL_REG.
If the device is operating in register-based manual clock selection mode
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input clock
will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00, the CS_CA
input pin continues to control clock selection and
00: CKIN_1 selected.
01: CKIN_2 selected.
10: Reserved
11: Reserved
DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic clock
selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of all of the
input clocks.
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (disabled)
during an internal calibration. See Table 3 on page 18.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
Reserved.
D6
DHOLD
R/W
D5
Preliminary Rev. 0.3
SQ_ICAL
R/W
D4
Function
D3
CKSEL_REG is of no consequence
D2
Reserved
R
D1
Si5324
.
D0
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