SI5324-EVB Silicon Laboratories Inc, SI5324-EVB Datasheet - Page 59

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SI5324-EVB

Manufacturer Part Number
SI5324-EVB
Description
BOARD EVALUATION SI5324
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5324-EVB

Main Purpose
Timing, Clock Multiplier
Embedded
No
Utilized Ic / Part
SI5324
Primary Attributes
2 Inputs, 2 Outputs
Secondary Attributes
CML, CMOS, LVDS, LVPECL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Si5324
D
Revision 0.1 to Revision 0.2
Revision 0.2 to Revision 0.25
Revision 0.25 to Revision 0.3
59
OCUMENT
Updated Rise/Fall Time values.
Updated minimum loop BW value.
Updated features and applications.
Changed maximum loop bandwidth to 525 Hz
(global).
Updated PLL performance specifications in Table 1.
Added Typical Video Phase Noise Plot and data.
Removed references to Si5325.
Added note to register CKOUT_ALWAYS_ON on
how to control output to output skew.
Added Product Selection Guide to Section “7.
Ordering Guide”.
Corrected typographical errors in Table 1.
Updated typical phase noise performance page.
Updated functional description.
Added additional phase noise plots to Section “2.
Typical Phase Noise Performance”.
Updated Register Map.
Revised Device Top Mark.
Changed Any-Rate to Any-Frequency
Changed Table 2, “Absolute Maximum Ratings,” on
page 6
Added Table 3, “CKOUT_ALWAYS_ON and
SQ_ICAL Truth Table,” on page 18
Added “no bypass with CMOS outputs”
C
HANGE
L
IST
Preliminary Rev. 0.3

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