EVAL-AD7677CBZ Analog Devices Inc, EVAL-AD7677CBZ Datasheet - Page 17

• Manufacturer Part Number: EVAL-AD7677CBZ
• Description: BOARD EVALUATION FOR AD7677
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7677CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 115mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7677
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL INTERFACE
The AD7677 is configured to use the serial interface when the
SER/PAR is held high. The AD7677 outputs 16 bits of data,
MSB first, on the SDOUT Pin. This data is synchronized with
the 16 clock pulses provided on the SCLK Pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7677 is configured to generate and provide the serial
data clock SCLK when the EXT/INT Pin is held low. The AD7677
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. The output data is valid on both the
rising and falling edge of the data clock. Depending on RDC/
SDIN input, the data can be read after each conversion, or during
the following conversion.
Figure 17 and Figure 18 show the detailed timing diagrams of
these two modes.
Usually, because the AD7677 is used with a fast throughput, the
mode master, read during conversion, is the most recommended
serial mode when it can be used.
REV. A
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
SDOUT
SDOUT
CNVST
BUSY
SCLK
BUSY
SCLK
SDIN
CS
CS
Figure 19. Slave Serial Data Timing for Reading (Read After Convert)
t
16
t
t
16
31
t
3
t
t
33
31
X
X
t
t
36
1
36
1
t
t
35
35
D15
X15
D15
t
t
37
t
37
34
2
2
EXT/INT = 1
X14
D14
EXT/INT = 1
D14
t
32
t
32
3
3
X13
D13
D13
–17–
In read-after-conversion mode, unlike in other modes, it should
be noted that the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase, which
results in a longer BUSY width.
In read-during-conversion mode, the serial clock and data toggle at
appropriate instances minimizes potential feedthrough between
digital activity and the critical conversion decisions.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
SLAVE SERIAL INTERFACE
External Clock
The AD7677 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/INT pin is held
high. In this mode, several methods can be used to read the
data. The external serial clock is gated by CS and the data are
output when both CS and RD are low. Thus, depending on CS,
the data can be read after each conversion or during the follow-
ing conversion. The external clock can be either a continuous
or discontinuous clock. A discontinuous clock can be either
INVSCLK = 0
14
INVSCLK = 0
14
15
15
D1
X1
D1
RD = 0
16
16
D0
X0
RD = 0
D0
17
X15
Y15
18
X14
Y14
AD7677