EVAL-AD7677CBZ Analog Devices Inc, EVAL-AD7677CBZ Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD7677CBZ
• Description: BOARD EVALUATION FOR AD7677
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7677CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 115mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7677
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7677
TIMING SPECIFICATIONS
Refer to Figures 11 and 12
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
Refer to Figures 17 and 18 (Master Serial Interface Modes)
Refer to Figures 19 and 20 (Slave Serial Interface Modes)
NOTES
1
2
3
Specifications subject to change without notice.
In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
In serial master read during convert mode. See Table I for serial master read after convert mode.
Convert Pulsewidth
Time Between Conversions
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read after Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulsewidth
CNVST LOW to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay (Read During Convert)
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH
Internal SCLK LOW
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read After Convert
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
3
3
3
3
3
3
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise stated.)
3
3
2
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
–4–
Min
5
1/1.25/1.5
10
250
10
45
5
3
25
12
7
4
2
3
5
3
5
5
25
10
10
L
of 10 pF; otherwise, the load is 60 pF maximum.
Typ
2
25/275/525
See Table I
0.75/1/1.25
25
Max
Note 1
30
0.75/1/1.25
0.75/1/1.25
0.75/1/1.25
40
15
10
10
10
40
10
10
10
18
REV. A
Unit
ns
µs
ns
µs
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns