CDB53L21 Cirrus Logic Inc, CDB53L21 Datasheet
CDB53L21
Specifications of CDB53L21
Related parts for CDB53L21
CDB53L21 Summary of contents
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Low Power, Stereo Analog to Digital Converter FEATURES 98 dB Dynamic Range (A-wtd) -88 dB THD+N Analog Gain Controls – + +16 dB MIC Pre-Amplifiers – Analog Programmable Gain Amplifier (PGA) +20 dB Digital Boost Programmable Automatic Level ...
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... The CS53L21 is available in a 32-pin QFN package in both Commercial (-10 to +70° C) and Automotive grades (-40 to +85° C). The CDB53L21 Customer Dem- onstration board is also available for device evaluation and implementation suggestions. Please see Information” on page 63 for complete details ...
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TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11 SPECIFIED OPERATING CONDITIONS ............................................................................................. 11 ABSOLUTE MAXIMUM RATINGS ...
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Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 40 6.2 Power Control 1 (Address 02h) ...................................................................................................... 40 6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 41 6.4 Interface Control (Address 04h) ..................................................................................................... 43 6.5 MIC ...
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Figure 21.AIN & PGA Selection ................................................................................................................ 47 Figure 22.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 56 Figure 23.ADC Passband Ripple .............................................................................................................. 60 Figure 24.ADC Stopband Rejection .......................................................................................................... 60 Figure 25.ADC Transition Band ................................................................................................................ 60 Figure 26.ADC Transition Band Detail ...................................................................................................... ...
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PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (I²S/LJ) AD0/CS (TSTN) VA_PULLUP TSTO AGND TSTO Pin Name # Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the 1 LRCK serial ...
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Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con- 9 TSTO nection external to the pin). 10 NIC .Not Internally Connected - This pin is not connected internal ...
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Digital I/O Pin Characteristics The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name I/O SW/(HW) RESET Input SCL/CCLK Input (I²S/LJ) SDA/CDIN Input/Output (MCLKDIV2) AD0/CS Input (DEM) MCLK Input LRCK ...
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TYPICAL CONNECTION DIAGRAMS +1 +2 µF 0.1 µF Digital Audio Processor Ω Ω +1.8 V, +2.5 V See Note 1 or +3.3 V 0.1 µF Note 1: Resistors are required for ...
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VL or DGND (1) Digital Audio Processor +1.8V, 2 +3.3V 0.1 µF Ω ≤ (1) Pull- (47 k for Master Mode. Pull-down to DGND for Slave Mode. Figure 2. ...
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CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25° C.) A SPECIFIED OPERATING ...
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ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) (Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive input filter; Measurement Bandwidth kHz unless otherwise specified. Sample Frequency = 48 kHz) ...
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ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input filter; Measurement Bandwidth kHz unless otherwise specified. Sample Frequency = 48 kHz) Parameter ...
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ADC DIGITAL FILTER CHARACTERISTICS Parameter Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics (48 kHz Fs) Frequency Response -3.0 dB -0.13 dB Phase Deviation @ 20 Hz Passband Ripple Filter Settling Time 6. Response ...
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Parameters Master Mode (Note 9) Output Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Edge to SDOUT MSB Output Delay SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge 7. After ...
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SWITCHING SPECIFICATIONS - I²C CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDA C Parameter SCL Clock Frequency RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) ...
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SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter CCLK Clock Frequency RESET Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High ...
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DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) Parameters VQ Characteristics Nominal Voltage Output Impedance DC Current Source/Sink (Note 14) FILT+ MIC BIAS Characteristics Nominal Voltage DC Current Source Power Supply Rejection Ratio (PSRR) Power ...
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POWER CONSUMPTION See (Note 17) Operation 1 Off (Note 18) 2 Standby (Note 19) ADC 1.8 3 Mono Record PGA to ADC ...
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APPLICATIONS 4.1 Overview 4.1.1 Architecture The CS53L21 is a highly integrated, low power, 24-bit audio A/D. The ADC operates at 64Fs, where Fs is equal to the system sample rate. The different clock rates maximize power savings while maintaining ...
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Hardware Mode A limited feature-set is available when the A/D powers up in Hardware Mode (see Up Sequence” on page 32) and may be controlled via stand-alone control pins. tions/features, the default configuration and the associated stand-alone control available. ...
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Analog Inputs AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level sig- nals, allowing various gain and signal adjustments for each channel. MUX MUX ADCA_HPF FREEZE ADCA_HPF ENABLE ALC_ARATE[5:0] ALC_RRATE[5:0] Σ MICMIX ...
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High-Pass Filter and DC Offset Calibration The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the high-pass filter is “frozen” during normal operation, the current value of the DC ...
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The MICBIAS series resistor must be selected based on the requirements of the particular microphone used. The MICBIAS output pin is selected using the MICBIAS_SEL bit. Software “Interface Control (Address 04h)” on page Controls Figure 8. MIC Input ...
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Analog Input Multiplexer A stereo 4-to-1 analog input multiplexer selects between a line-level input source mic-level input source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or by- passed around the PGA. ...
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Automatic Level Control (ALC) When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases the digital attenuation ...
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Noise Gate The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before ...
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Signal Processing Engine The SPE provides various signal processing functions that apply to the ADC data. Software “SPE Control (Address 09h)” on page 48 Controls: INPUTS FROM ADCA and ADCB 4.4.1 Volume Controls The digital volume control functions offer ...
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Serial Port Clocking The A/D serial audio interface port operates either as a slave or master. It accepts externally generated clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in master mode. ...
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Slave LRCK and SCLK are inputs in Slave Mode. The speed of the A/D is automatically determined based on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two ...
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High-Impedance Digital Output The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O with- out the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O ...
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LRCK L eft SCLK SDIN AOUTA / AINxA 4.7 Initialization The initialization and Power-Down sequence flowchart is shown in Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma ...
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Recommended Power-Down Sequence To minimize audible pops when turning off or placing the A/D in standby, 1. Mute the ADC’s. 2. Set the PDN bit in the power control register to ‘1’b. The A/D will not power down until ...
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Software Mode The control port is used to access the registers allowing the A configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio ...
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MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS53L21 after each input byte is read and is input to the CS53L21 ...
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Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details. 4.10.3.1 Map Increment (INCR) The device has MAP auto-increment ...
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REGISTER QUICK REFERENCE Software mode register defaults are as shown. “Reserved” registers must maintain their default state. Addr Function 7 01h ID Chip_ID4 Chip_ID3 default 02h Power Ctl. 1 Reserved Reserved 1(See Note ...
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Addr Function default 0Eh Vol. Control MUTE_ADC ADCMIXA MIXA ADCMIXA default 0Fh Vol. Control MUTE_ADC ADCMIXB MIXB ADCMIXB default 10h Reserved Reserved Reserved 1 default 11h Reserved Reserved Reserved 1 ...
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Addr Function 7 1Dh ALC Release Reserved Reserved Rate default 1Eh ALC Thresh- MAX2 old default 1Fh Noise Gate NG_ALL NG_EN Config default 20h Status Reserved SP_CLK default ...
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REGISTER DESCRIPTION All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after ...
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Power Down PGA X (PDN_PGAX) Default Disable 1 - Enable Function: PGA channel x will either enter a power-down or muted state when this bit is enabled. See 1 (Address 02h) Note 1 above. This bit is ...
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Speed Mode (SPEED[1:0]) Default Quarter-Speed Mode (QSM 12.5 kHz sample rates 10 - Half-Speed Mode (HSM kHz sample rates 01 - Single-Speed Mode (SSM kHz sample ...
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Interface Control (Address 04h Reserved M/S Reserved Master/Slave Mode (M/S) Default Slave 1 - Master Function: Selects either master or slave operation for the serial port. DS700PP1 Reserved Reserved CS53L21 2 ...
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ADC I²S or Left-Justified (ADC_I²S/LJ) Default Left-Justified 1 - I²S Function: Selects either the I²S or Left-Justified digital interface format for the data on SDOUT. The required relation- ship between the Left/Right clock, serial clock and serial ...
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ADCx 20 dB Digital Boost (ADCx_DBOOST) Default Disabled 1 - Enabled Function: Applies digital gain to the input signal on ADC channel x, regardless of the input path. MIC Bias Select (MICBIAS_SEL) Default: 0 ...
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ADCX High-Pass Filter Freeze (ADCX_HPFRZ) Default Continuous DC Subtraction 1 - Frozen DC Subtraction Function: The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the decimation filter. If the ...
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ADCx Input Select, Invert & Mute (Address 07h AINB_MUX1 AINB_MUX0 AINA_MUX1 ADCX Input Select Bits (AINX_MUX[1:0]) Default: 00 PDN_PGAx AINx_MUX[1: Function: ...
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SPE Control (Address 09h Reserved SPE_ENABLE FREEZE SPE_ENABLE Default Reserved 1 - ADC Serial Port to SPE Function: Selects the digital signal source for the SPE. Note: If DIGMIX = 1, SPE_ENABLE must be ...
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SPE Soft Ramp and Zero Cross Control (SPE_SZC[1:0]) Default = Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Note: The SPE_ENABLE bits in reg09h must be set ...
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ALCX Zero Cross Disable (ALCX_ZCDIS) Default Off Function: Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the ...
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Function: The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from 0 to -96 dB. Levels are decoded in two’s complement, as shown in the ...
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ADCA[1:0] SDOUT ----------- - Function: Implements mono mixes of the left and right channels as well as a left/right channel swap. 6.13 ALC Enable & Attack Rate (Address 1Ch ALC_ENB ...
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Function: Sets the rate at which the ALC releases the PGA & digital attenuation from levels below the minimum setting in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] & ADCx_ATT[7:0] setting. The ALC release rate ...
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Noise Gate Configuration & Misc. (Address 1Fh NG_ALL NG_EN NG_BOOST Noise Gate Channel Gang (NG_ALL) Default Disabled 1 - Enabled Function: Gangs the noise gate function for channel A and B. When enabled, both ...
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Status (Address 20h) (Read Only Reserved SP_CLKERR Reserved For all bits in this register, a “1” means the associated error condition has occurred at least once since the register was last read. A ”0” means the associated ...
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... ADC_FILT+ Capacitor Effects on THD+N The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion + noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N at low frequencies. Figure 22 en from the CDB53L21 using an Audio Precision analyzer. -60 -64 -68 -72 ...
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EXAMPLE SYSTEM CLOCK FREQUENCIES 8.1 Auto Detect Enabled Sample Rate LRCK (kHz) 8 11.025 12 Sample Rate LRCK (kHz) 16 22.05 24 Sample Rate LRCK (kHz) 32 44.1 48 Sample Rate LRCK (kHz) 64 88.2 96 *The”MCLKDIV2” pin 4 ...
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Auto Detect Disabled Sample Rate LRCK (kHz) 512x 8 - 11.025 - 12 6.1440 Sample Rate LRCK (kHz) 256x 16 - 22. 6.1440 Sample Rate LRCK (kHz) 32 44.1 48 Sample Rate LRCK (kHz) 64 88.2 96 ...
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PCB LAYOUT CONSIDERATIONS 9.1 Power Supply, Grounding As with any high-resolution converter, the CS53L21 requires careful attention to power supply and ground- ing arrangements if its potential performance realized. power arrangements, with VA connected to a ...
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FILTERS Figure 23. ADC Passband Ripple Figure 25. ADC Transition Band 60 Figure 24. ADC Stopband Rejection Figure 26. ADC Transition Band Detail CS53L21 DS700PP1 ...
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DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with ...
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DIMENSIONS 32L QFN ( BODY) PACKAGE DRAWING D Pin #1 Corner Top View INCHES DIM MIN 0.0000 b 0.0071 0.0091 D 0.1969 BSC D2 0.1280 0.1299 E 0.1969 BSC E2 0.1280 0.1299 e ...
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... Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com DS700PP1 Package Pb-Free Grade Temp Range Commercial -10 to +70° C 32L-QFN Yes Automotive -40 to +85° CS53L21 Container Order # Rail CS53L21-CNZ Tape & Reel CS53L21-CNZR Rail CS53L21-DNZ Tape & Reel CS53L21-DNZR - - CDB53L21 63 ...
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HISTORY Revision A1 Initial Release Adjusted the minimum voltage specification in Adjusted maximum “Analog In to PGA to ADC” THD+N performance specification in (Commercial - CNZ)” on page Corrected Interchannel Gain Mismatch specification in and “Analog Characteristics (Automotive - ...
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Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full ...
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CS53L21 DS700PP1 ...