CDB53L21 Cirrus Logic Inc, CDB53L21 Datasheet - Page 55

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CDB53L21

Manufacturer Part Number
CDB53L21
Description
BOARD EVAL FOR CS53L21 ADC
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB53L21

Number Of Adc's
2
Number Of Bits
24
Sampling Rate (per Second)
96k
Data Interface
Serial
Inputs Per Adc
3 Single Ended
Input Range
±2.5 V
Power (typ) @ Conditions
22.45mW @ 48kSPS, 2.5 V
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Utilized Ic / Part
CS53L21
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1550
DS700PP1
6.17
Reserved
7
Status (Address 20h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A ”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: 0
Function:
Indicates an invalid MCLK to LRCK ratio. See
page 29
Note:
ADC Overflow (ADCX_OVFL)
Default = 0
Function:
Indicates that there is an over-range condition anywhere in the CS53L21 ADC signal path of each of the
associated ADC’s.
SP_CLKERR
for valid clock ratios.
On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
6
Reserved
5
Reserved
4
“Serial Port Clocking” on page 29“Serial Port Clocking” on
Reserved
3
Reserved
2
ADCA_OVFL
1
CS53L21
ADCB_OVFL
0
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