CDB53L21 Cirrus Logic Inc, CDB53L21 Datasheet
CDB53L21
Specifications of CDB53L21
Related parts for CDB53L21
CDB53L21 Summary of contents
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... MCLK Oscillator (socket) http://www.cirrus.com Description The CDB53L21 evaluation board is an excellent means for evaluating the CS53L21 ADC. Evaluation requires an analog audio source, an analog/digital analyzer and power supplies. Optionally, a Windows PC-compatible computer may be used to evaluate the CS53L21 in Soft- ware Mode. ...
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... Mix Volume Controls Tab ............................................................................................................... 11 2.5 Register Maps Tab ......................................................................................................................... 12 3. HARDWARE MODE CONTROL .......................................................................................................... 13 3.1 FPGA H/W Control ......................................................................................................................... 13 3.2 CS53L21 H/W Control .................................................................................................................... 16 4. PERFORMANCE PLOTS ..................................................................................................................... 17 5. SYSTEM CONNECTIONS AND JUMPERS ........................................................................................ 20 6. BLOCK DIAGRAM ............................................................................................................................... 22 7. SCHEMATICS ...................................................................................................................................... 23 8. BOARD LAYOUT ................................................................................................................................. 30 9. REVISION HISTORY ............................................................................................................................ 33 2 CDB53L21 DS700DB1 ...
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... Figure 32.Control Port I/O (Schematic Sheet 5) ....................................................................................... 28 Figure 33.Power (Schematic Sheet 6)lm .................................................................................................. 29 Figure 34.Silk Screen ................................................................................................................................ 30 Figure 35.Top-Side Layer ......................................................................................................................... 31 Figure 36.Bottom-Side Layer .................................................................................................................... 32 LIST OF TABLES Table 1. MCLK and Clock/Data Routing Options ...................................................................................... 13 Table 2. CS53L21 H/W Mode Control ....................................................................................................... 16 Table 3. System Connections ................................................................................................................... 20 Table 4. Jumper Settings .......................................................................................................................... 21 DS700DB1 CDB53L21 3 ...
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... SYSTEM OVERVIEW The CDB53L21 evaluation board is an excellent means for evaluating the CS53L21 ADC. Digital audio signal out- puts are provided, and an FPGA is used for easily configuring the board. page 7 and Section 3. “Hardware Mode Control” on page 13 The CDB53L21 schematic set has been partitioned into seven pages and is shown in tem Connections and Jumpers” ...
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... DS700DB1 (Figure 29 on page Section 3. “Hardware Mode Control” on page 13 Section 2. “Software Mode Control” on page 7 provide configuration details. in the schematic set illustrates how signals are routed. CDB53L21 25) and a discussion of the digital au- Section 2. “Software provide configuration details. and Section 3. (Figure 31 on page 27). Selections Section 2. “ ...
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... Section 3. “Hardware Mode Control” on page 13 1.10 Control Port Connectors A graphical user interface is available for the CDB53L21, allowing easy manipulation of each register. This GUI interfaces with the CDB via the RS-232 or USB connectors and controls all Software Mode options. Section 2. “Software Mode Control” on page 7 1 ...
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... Set up the CS53L21 in the “ADC Configuration”, “ADC Volume Controls” or “Mix Volume Controls” tab as desired. 10. Begin evaluating the CS53L21. For quick setup, the CDB53L21 may, alternatively, be configured by loading a predefined sample script file: 11. On the File menu, click "Restore Board Registers..." 12. Browse to Boards\CDB53L21\Scripts\. ...
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... General Configuration Tab The “General Configuration” tab provides high-level control of signal routing on the CDB53L21. This tab also includes basic controls for the CS53L21 for quickly setting up the CDB53L21 in simple configurations. Sta- tus text detailing the ADC’s specific configuration is shown in parenthesis or appears directly below the as- sociated control ...
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... Serial Port Configuration - Includes controls for all settings related to the transmission and relationship of data and clocks within the CS53L21. Update - Reads all registers in the CS53L21 and reflects the current values in the GUI. Reset - Resets the CS53L21. DS700DB1 Figure 2. ADC Configuration Tab CDB53L21 9 ...
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... Analog Volume Control - Includes all analog volume controls and adjustments for the ADC. Noise Gate Configuration - Includes all configuration settings for the noise gate. Update - Reads all registers in the CS53L21 and reflects the current values in the GUI. Reset - Resets the CS53L21. 10 Figure 3. ADC Volume Controls Tab CDB53L21 DS700DB1 ...
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... CS53L21 data sheet): Digital Volume Control - ADC channel mix volume controls and adjustments. Update - Reads all registers in the CS53L21 and reflects the current values in the GUI. Reset - Resets the CS53L21. DS700DB1 Figure 4. Mix Volume Controls Tab CDB53L21 11 ...
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... Register values can be modified bit-wise or byte-wise. For bit-wise, click the appropriate push-button for the desired bit. For byte-wise, the desired hex value can be typed directly into the register address box in the register map. The “FPGA” and “GPIO” tabs may be ignored. 12 Figure 5. Register Maps Tab - CS53L21 CDB53L21 DS700DB1 ...
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... Control” and “CS53L21 H/W Control.” These switches are enabled in Hardware Mode only and ignored in Software Mode. The CDB53L21 automatically enters Hardware Mode upon initial power up, or when exiting Software Mode, by terminating the Cirrus FlexGUI software or by disconnecting the RS-232 serial cable or USB cable. ...
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... CS8406 I/O Header CS8406 I/O Header 14 Oscillator CS53L21 MCLK LRCK/SCLK OMCK (256Fs) ILRCK/ ISCLK SDIN (LJ) MCLK LRCK/SCLK SDOUT Figure 6. Routing 4 Oscillator CS53L21 MCLK LRCK/SCLK OMCK (256Fs) ILRCK/ ISCLK SDIN (LJ) MCLK LRCK/SCLK SDOUT Figure 7. Routing 6 CDB53L21 SDOUT SDOUT DS700DB1 ...
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... DS700DB1 Oscillator MCLK LRCK/SCLK CS8406 OMCK (256Fs) ILRCK/ ISCLK SDIN (LJ) I/O Header MCLK LRCK/SCLK SDOUT Figure 8. Routing 8 Oscillator MCLK LRCK/SCLK CS8406 OMCK (256Fs) ILRCK/ ISCLK SDIN (LJ) I/O Header MCLK LRCK/SCLK SDOUT Figure 9. Routing 10 CDB53L21 CS53L21 SDOUT CS53L21 SDOUT 15 ...
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... LRCK and SCLK are inputs to CS53L21. LRCK and SCLK are outputs to CS53L21. Internal MCLK to CS53L21 not divided. Internal MCLK to CS53L21 divided by 2. CS53L21 Interface Format: Left-Justified. CS53L21 Interface Format: I²S. Table 2. CS53L21 H/W Mode Control CDB53L21 Control” in the “FPGA H/W DS700DB1 ...
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... Figure 13. -60 dB FFT, Double-Speed Mode +0 -10 -20 -30 -40 -50 -60 - -100 -110 -120 -130 -140 -150 -160 -170 -180 2k 5k 10k 20k 20 Figure 15. No Input FFT, Double-Speed Mode CDB53L21 50 100 200 500 10k Hz 50 100 200 500 10k Hz 50 100 200 500 10k Hz 20k 20k ...
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... Figure 17. THD+N vs. Frequency, Double-Speed Mode -80 -82 -84 - -92 -94 -96 -98 -100 -40 -30 -20 -10 -120 -100 Figure 19. THD+N vs. Amplitude, Double-Speed Mode + -10 -40 -20 +0 -140 -120 Figure 21. Fade-to-Noise Linearity, Double-Speed Mode CDB53L21 100 200 500 10k Hz -80 -60 -40 -20 dBr -100 -80 -60 -40 -20 dBr DS700DB1 20k +0 ...
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... DS700DB1 +0 -0.2 -0.4 -0.6 -0 -1.2 -1.4 -1.6 -1 10k 20k - Figure 23. Frequency Response, Double-Speed Mode +0 -10 -20 -30 - -60 S -70 -80 -90 -100 -110 2k 5k 10k 20k 20 50 Figure 25. Channel Crosstalk, Double-Speed Mode CDB53L21 100 200 500 100 200 500 10k Hz 10k 20k 20k 19 ...
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... Reset for the micro controller (U84). Input Reload Xilinx Flash program into the FPGA (U14). Input Reset for the CS53L21 (U1). Input RCA phono jacks for analog input signal to CS53L21. Input Microphone jacks for analog input signal to CS53L21. Table 3. System Connections CDB53L21 SIGNAL PRESENT DS700DB1 ...
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... MIC2 signal routed to AIN3A of ADC. MIC1 MIC1 signal routed to AIN3A of ADC. *LINEA LINEA MUX routed to AIN3A of ADC. BIAS1 J3 (for Bias on AIN2B of ADC) routed to MIC2. BIAS2 J8 (for Bias on AIN3B of ADC) routed to MIC2. *Not con- Jumper placed on pin 2. nected *Default factory settings Table 4. Jumper Settings CDB53L21 21 ...
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BLOCK DIAGRAM Hardware Mode Software Mode Figure 27 on page 23 Control Port Reset Figure 32 on page 28 S/PDIF Out (CS8406) Figure 29 on page 25 MCLK Oscillator (socket) Figure 31 on page 27 Switches I²C/SPI Header Figure ...
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SCHEMATICS Figure 27. CS53L21 (Part of Schematic Sheet 1) ...
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Figure 28. Analog I/O (Part of Schematic Sheet 1) ...
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Figure 29. S/PDIF I/O (Schematic Sheet 2) ...
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Figure 30. FPGA (Schematic Sheet 3) ...
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Figure 31. Level Shifters & I/O Stake Header (Schematic Sheet 4) ...
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Figure 32. Control Port I/O (Schematic Sheet 5) ...
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Figure 33. Power (Schematic Sheet 6)lm ...
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... BOARD LAYOUT CDB53L21 CS53L21 CS53L21 CS53L21 Figure 34. Silk Screen ...
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Figure 35. Top-Side Layer ...
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Figure 36. Bottom-Side Layer ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. Windows is a registered trademark of Microsoft Corporation. DS700DB1 Changes www.cirrus.com CDB53L21 33 ...