CDB53L21 Cirrus Logic Inc, CDB53L21 Datasheet - Page 29

• Manufacturer Part Number: CDB53L21
• Description: BOARD EVAL FOR CS53L21 ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB53L21

• Number Of Adc's: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 96k
• Data Interface: Serial
• Inputs Per Adc: 3 Single Ended
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 22.45mW @ 48kSPS, 2.5 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS53L21
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1550

DS700PP1
4.5
Serial Port Clocking
The A/D serial audio interface port operates either as a slave or master. It accepts externally generated
clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in
master mode.
The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate,
Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked
into or out of the device.
The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S) and MCLKDIV2 stand-alone control
pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in
Slave Mode. The value on the SDOUT pin is latched immediately after powering up in Hardware Mode.
Hardware
Software
Control:
Control:
“MIC Power Control & Speed Control (Address 03h)” on page
(Address 09h)” on page
“SDOUT, M/S” pin 29
“MCLKDIV2” pin 2
Pin
48.
47 kΩ Pull-down
47 kΩ Pull-up
Setting
LO
HI
Slave
Master
No Divide
MCLK is divided by 2 prior
to all internal circuitry.
41,
“SPE Control
Selection
CS53L21
29