HI7190EVAL Intersil, HI7190EVAL Datasheet
HI7190EVAL
Specifications of HI7190EVAL
Related parts for HI7190EVAL
HI7190EVAL Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-3774 All other trademarks mentioned are the property of their respective owners. HI7190 FN3612.10 | Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved. ...
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... HI7190IBZ-T HI7190IBZ - (Note) HI7190EVAL Evaluation Kit *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Typical Application Schematic +5V INPUT + - INPUT REFERENCE -5V 0.1μF 3 HI7190 10MHz 17 16 OSC OSC 4.7μF 0.1μ INHI 11 V INLO +2.5V V RHI ...
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Absolute Maximum Ratings Supply Voltage AV to AGND ...
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Electrical Specifications AV DD PGIA Gain = 1, OSC PARAMETER Input Capacitance DIGITAL OUTPUTS Output Logic High Voltage Output Logic Low Voltage Output Three-State Leakage Current Digital Output Capacitance, C OUT TIMING ...
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Timing Diagrams t PRE CS SCLK SDIO CS SCLK SDIO SDO t ACC DRDY CS SCLK SDIO 1 6 HI7190 t SCLK t DSU t t SCLKPW SCLKPW t DHLD 1ST BIT FIGURE 1. DATA WRITE TO HI7190 1ST BIT ...
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Pin Descriptions 20 LEAD DIP, SOIC PIN NAME 1 SCLK Serial Interface Clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the falling edge. 2 SDO Serial Data OUT. Serial data is read from ...
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TABLE 1. NOISE PERFORMANCE WITH INPUTS CONNECTED TO ANALOG GROUND P-P NOISE HERTZ SNR ENOB GAIN = 1 10 132.3 21.7 25 129.5 21.2 30 127.7 20.9 50 126.3 20.7 60 125.6 20.6 100 122.4 20.0 250 107.7 17.6 500 ...
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Definitions Integral Non-Linearity, INL, is the maximum deviation of any digital code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale (a point 0.5 LSB below the first ...
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SPI and Intel 8051 series SSR protocols. Data Integrity is always maintained at the HI7190 output port. This means that if a data read of conversion N is begun but not finished before the next conversion (conversion ...
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The feedback loop forces the average of the fed back signal to be equal to the input signal V PGIA INTEGRATOR + ∑ ∫ DAC V RHI V RLO FIGURE 6. SIMPLE MODULATOR BLOCK DIAGRAM Analog ...
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AV - 1.8V. Exceeding this range on the V DD compromise the device performance. Transducer Burn-Out Current Source The V input of the HI7190 contains a 500nA (Typ) current INHI source which can be turned on/off via the Control Register. ...
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Instead, there is a small h probability erroneous negative full scale (000000 output. Refer to Technical Brief TB348 for complete details. The FP10 to FP0 bits programmed into the Control Register determine the ...
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The HI7190 offers several different modes of Self-Calibration and System Calibration. For calibration to occur, the on-chip microcontroller must convert the modulator output for three different input conditions - “zero-scale,” “positive full scale,” and “negative full scale”. With these readings, ...
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System Offset/Internal Gain Calibration Mode Please note: System Offset/Internal Gain is only valid when operating in a gain of one. In addition, the offset and gain errors are not reduced as with the full system calibration. The System Offset/Internal Gain ...
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SCLK transition output is delayed 29 OSC the next rising OSC . SCLK transitions eight times and then 1 stalls high for 28 OSC cycles. After this stall period is 1 completed SCLK will again transition eight times and ...
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DRDY - Data Ready. This is an output status flag from the device to signal that the Data Output Register has been updated with the new conversion result. DRDY is useful as an edge or level sensitive interrupt signal to ...
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Instruction Register The Instruction Register is an 8-bit register which is used during a communications cycle for setting up read/write operations. INSTRUCTION REGISTER MSB R/W MB1 MB0 FSC A3 R/W - Bit 7 of the Instruction ...
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The communication cycle is started by asserting the CS line and starting the clock from its idle state. To assert a read cycle, during the instruction phase of the communication cycle, the Instruction Byte should be set to a read ...
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IR WRITE PHASE CS SCLK SDIO SDO FIGURE 17. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE HIGH IR WRITE PHASE CS SCLK SDIO SDO THREE-STATE FIGURE 18. ...
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Changing the filter notch frequency, as well as the selected gain, impacts resolution. The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch to the filter. For example, if ...
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data overwriting conversion X results. For example, with f = 10MHz, f OSC read cycle must start within 1/2000 - 128(1/10 after DRDY went low. 2) The Data Output Register read cycle for conversion ...
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Die Characteristics DIE DIMENSIONS 3550μm x 6340μm METALLIZATION Type: AlSiCu Å Thickness:Metal 2, 16k Å Metal 1, 6k Metallization Mask Layout CS DRDY DGND HI7190 SUBSTRATE POTENTIAL (POWERED UP PASSIVATION Type: Sandwich Å Thickness:Nitride 8k ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...