HI7190EVAL Intersil, HI7190EVAL Datasheet - Page 20

• Manufacturer Part Number: HI7190EVAL
• Description: EVALUATION PLATFORM HI7190
• Manufacturer: Intersil

Specifications of HI7190EVAL

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 15mW @ 200kSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: HI7190
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Control Register
The Control Register contains 24-bits to control the various
sections of the HI7190. This register is a read/write
register.
MSB
FP3
DC
SDIO
G2
SCLK
15
SDO
SCLK
SCLK
7
SDIO
SDIO
SDO
SDO
CS
CS
CS
FP10
FP2
I0
G1
22
14
6
I0
I0
I1
I1
FP9
FP1
G0
I1
21
13
5
I2
IR WRITE PHASE
IR WRITE PHASE
IR WRITE PHASE
I2
I2
I3
THREE-STATE
THREE-STATE
FP8
FP0
I3
BO
20
12
I3
4
I4
BYTE 2
BYTE 1
BYTE 0
FIGURE 18. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE LOW
FIGURE 17. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE HIGH
FIGURE 19. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE HIGH
20
I4
I4
I5
MD2
FP7
SB
19
11
I5
3
I5
I6
I6
I6
I7
MD1
FP6
BD
18
10
2
I7
I7
MD0
MSB
FP5
17
B0
9
1
B0
B0
LSB
SDL
FP4
B/U
B1
16
8
B1
B1
B2
HI7190
B2
B2
B3
B3
B3
B4
DC - Bit 23 is the Data Coding Bit used to select between
two’s complementary and offset binary data coding. When
this bit is set (DC = 1) the data in the Data Output Register
will be two’s complement. When cleared (DC = 0) this data
will be offset binary. When operating in the unipolar mode
the output data is available in straight binary only (the DC bit
is ignored). This bit is cleared after a RESET is applied to the
part.
FP10 through FP0 - Bits 22 through 12 are the Filter
programming bits that determine the frequency response of
the digital filter. These bits determine the filter cutoff
frequency, the position of the first notch and the data rate of
the HI7190. The first notch of the filter is equal to the
decimation rate and can be determined by the formula:
f
where CODE is the decimal equivalent of the value in FP10
through FP0. The values that can be programmed into these
bits are 10 to 2047 decimal, which allows a conversion rate
range of 9.54Hz to 1.953kHz when using a 10MHz clock.
B4
NOTCH
B4
DATA TRANSFER PHASE - TWO-BYTE READ
B5
DATA TRANSFER PHASE - TWO-BYTE READ
DATA TRANSFER PHASE - TWO-BYTE READ
B5
B5
B6
= f
B6
THREE-STATE
B6
OSC
B7
THREE-STATE
/(512 x CODE)
B7
B7
B8
B8
B8
B9
B9
B9
B10
B10 B11 B12 B13 B14
B10 B11 B12 B13 B14
B11 B12 B13 B14
June 27, 2006
B15
B15
FN3612.10
B15