CDB43L21 Cirrus Logic Inc, CDB43L21 Datasheet
CDB43L21
Specifications of CDB43L21
Related parts for CDB43L21
CDB43L21 Summary of contents
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... MCLK Oscillator (socket) http://www.cirrus.com Description The CDB43L21 evaluation board is an excellent means for evaluating the CS43L21 DAC. Evaluation requires a digital signal source, analog analyzer, and power sup- plies. Optionally, a Windows PC-compatible computer may be used to evaluate the CS43L21 in Software Mode. ...
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... Register Maps Tab ......................................................................................................................... 10 3. HARDWARE MODE CONTROL .......................................................................................................... 11 3.1 FPGA H/W Control ......................................................................................................................... 11 3.2 CS43L21 H/W Control ................................................................................................................... 11 4. SYSTEM CONNECTIONS .................................................................................................................... 14 5. JUMPER SETTINGS ............................................................................................................................ 14 6. CDB43L21 BLOCK DIAGRAM ............................................................................................................ 15 7. CS43L21 SCHEMATICS ...................................................................................................................... 16 8. CDB43L21 LAYOUT ............................................................................................................................ 22 9. ERRATA ............................................................................................................................................... 25 10. REVISION HISTORY .......................................................................................................................... 25 1. SYSTEM OVERVIEW ............................................................................................................................. 4 1.1 Power ............................................................................................................................................... 4 1 ...
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... Figure 14.Control Port I/O (Schematic Sheet 5) ....................................................................................... 20 Figure 15.Power (Schematic Sheet 6) ...................................................................................................... 21 Figure 16.Silk Screen ................................................................................................................................ 22 Figure 17.Top-Side Layer ......................................................................................................................... 23 Figure 18.Bottom-Side Layer .................................................................................................................... 24 LIST OF TABLES Table 1. MCLK and Clock/Data Routing Options ...................................................................................... 11 Table 2. CS43L21 H/W Mode Control ....................................................................................................... 11 Table 3. System Connections ................................................................................................................... 14 Table 4. Jumper Settings .......................................................................................................................... 14 DS723DB1 CDB43L21 3 ...
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... SYSTEM OVERVIEW The CDB43L21 evaluation board is an excellent means for evaluating the CS43L21. Digital audio signal interfaces are provided, and an FPGA is used for easily configuring the board. and Section 3. “Hardware Mode Control” on page 11 The CDB43L21 schematic set has been partitioned into six pages and is shown in Connections” ...
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... DS723DB1 and Section 3. “Hardware Mode Control” on page 11 (Figure 12 on page Section 3. “Hardware Mode Control” on page 11 Section 2. “Software Mode Control” on page 7 provide configuration details. CDB43L21 provide 18) and a discussion of the digital audio Section 2. “Software provide configuration details. and Section 3. (Figure 13 on page 19). Selections Section 2. “ ...
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... Section 3. “Hardware Mode Control” on page 11 1.10 Control Port Connectors A graphical user interface is available for the CDB43L21, allowing easy manipulation of each register. This GUI interfaces with the CDB via the RS-232 connector and controls all Software Mode options. “Software Mode Control” on page 7 1 ...
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... Set up the CS43L21 in the “General Configurations” and “DAC Volume Controls” tab as desired. 10. Begin evaluating the CS43L21. For quick setup, the CDB43L21 may be configured by loading a predefined sample script file: 11. On the File menu, click "Restore Board Registers..." 12. Browse to Boards\CDB43L21\Scripts\. ...
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... General Configuration Tab The “General Configuration” tab provides high-level control of signal routing on the CDB43L21. This tab also includes basic controls for the CS43L21 for quickly setting up the CDB43L21 in simple configurations. Sta- tus text detailing the CS43L21’s specific configuration is shown in parenthesis or appears directly below the associated control ...
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... Tone Control - Includes all bass and treble boosting controls and adjustments. BEEP Generator - Includes all configuration settings for the BEEP generator. Update - Reads all registers in the CS43L21 and reflects the current values in the GUI. Reset - Resets the CS43L21. DS723DB1 Figure 2. DAC Volume Controls Tab CDB43L21 9 ...
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... Register values can be modified bit-wise or byte-wise. For bit-wise, click the appropriate push-button for the desired bit. For byte-wise, the desired hex value can be typed directly into the register address box in the register map. The “FPGA” and “GPIO” tabs may be ignored. 10 Figure 3. Register Maps Tab - CS43L21 CDB43L21 DS723DB1 ...
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... Control” and “CS43L21 H/W Control.” These switches are enabled in Hardware Mode only and ignored in Software Mode. The CDB43L21 automatically enters Hardware Mode upon initial power up, when exiting Software Mode, upon termination of the Cirrus FlexGUI software disconnecting the RS-232 serial cable. ...
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... OLRCK/ LRCK/SCLK OSCLK SDOUT SDIN (LJ) I/O Header MCLK LRCK/SCLK SDIN CS8415 CS43L21 RMCK MCLK (256Fs) OLRCK/ LRCK/SCLK OSCLK SDOUT SDIN (LJ) I/O Header MCLK LRCK/SCLK SDIN CDB43L21 Oscillator CS43L21 MCLK LRCK/SCLK SDIN Figure 5. Routing 2 Oscillator CS43L21 MCLK LRCK/SCLK SDIN Figure 7. Routing 4 DS723DB1 ...
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... CS8415 I/O Header DS723DB1 Oscillator CS43L21 RMCK MCLK (256Fs) OLRCK/ LRCK/SCLK OSCLK SDOUT SDIN (LJ) MCLK LRCK/SCLK SDIN Figure 8. Routing 5 CDB43L21 13 ...
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... AOUTB (LPF) Connects lowpass filtered AOUTA to RIGHT RCA jack 16 Ω resistor shunted from AOUTA to GND SHUNTED *Not con- Jumper placed on pin 1 nected 16 Ω resistor shunted from AOUTB to GND SHUNTED *Not con- Jumper placed on pin 1 nected regarding jumper settings for J31. Table 4. Jumper Settings CDB43L21 SIGNAL PRESENT FUNCTION SELECTED DS723DB1 ...
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... CDB43L21 BLOCK DIAGRAM Software Mode Control Port Reset Hardware Mode Switches S/PDIF Input FPGA (CS8415) Reset MCLK Oscillator (socket) I²C/SPI Header Reset MCLK CS43L21 Reset Clocks/Data Header Figure 9. Block Diagram Analog Output (Line + Headphone) ...
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CS43L21 SCHEMATICS Figure 10. CS43L21 and Analog I/O (Schematic Sheet 1) ...
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Figure 11. S/PDIF I/O (Schematic Sheet 2) ...
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Figure 12. FPGA (Schematic Sheet 3) ...
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Figure 13. Level Shifters & I/O Stake Header (Schematic Sheet 4) ...
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Figure 14. Control Port I/O (Schematic Sheet 5) ...
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Figure 15. Power (Schematic Sheet 6) ...
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... CDB43L21 LAYOUT CDB43L21 CS43L21 CS43L21 CS43L21 Figure 16. Silk Screen ...
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Figure 17. Top-Side Layer ...
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Figure 18. Bottom-Side Layer ...
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... ERRATA The CDB43L21 currently does not support the +1.8 V and +2.5 V power supply options on header J31 (VL). This header must be set to +3 ensure correct board operation. This issue is not device related; the allowed voltage levels are specified in the CS43L21 data sheet. 10.REVISION HISTORY ...