EVAL-ADUC824QS Analog Devices Inc, EVAL-ADUC824QS Datasheet - Page 30

• Manufacturer Part Number: EVAL-ADUC824QS
• Description: KIT DEV FOR ADUC824 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: 8052-corer

Specifications of EVAL-ADUC824QS

• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADuC824
OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers )
These three 8-bit registers hold the 24-bit offset calibration coefficient for the Primary ADC. These registers are configured at power-
on with a factory default value of 800000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration is initiated by the user via MD2–0 bits in the ADCMODE register.
SFR Address
Power-On Default Value
Bit Addressable
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers )
These two 8-bit registers hold the 16-bit offset calibration coefficient for the Auxiliary ADC. These registers are configured at power-on
with a factory default value of 8000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration is initiated by the user via the MD2–0 bits in the ADCMODE register.
SFR Address
Power-On Default Value
Bit Addressable
GN0H/GN0M/GN0L (Primary ADC Gain Calibration Registers )
These three 8-bit registers hold the 24-bit gain calibration coefficient for the Primary ADC. These registers are configured at power-on
with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these
bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in the
ADCMODE register.
SFR Address
Power-On Default Value
Bit Addressable
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers )
These two 8-bit registers hold the 16-bit gain calibration coefficient for the Auxiliary ADC. These registers are configured at power-on
with a factory calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these
bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in the
ADCMODE register.
SFR Address
Power-On Default Value
Bit Addressable
These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.
OF0H
OF0M
OF0L
800000H
No
OF1H
OF1L
8000H
No
GN0H
GN0M
GN0L
No
GN1H
GN1L
No
Primary ADC Offset Coefficient High Byte
Primary ADC Offset Coefficient Middle Byte
Primary ADC Offset Coefficient Low Byte
OF0H, OF0M, and OF0L, Respectively
All Three Registers
Auxiliary ADC Offset Coefficient High Byte
Auxiliary ADC Offset Coefficient Low Byte
OF1H and OF1L Respectively
Both Registers
Primary ADC Gain Coefficient High Byte
Primary ADC Gain Coefficient Middle Byte
Primary ADC Gain Coefficient Low Byte
Configured at factory final test, see notes above.
All Three Registers
Auxiliary ADC Gain Coefficient High Byte
Auxiliary ADC Gain Coefficient Low Byte
Configured at factory final test, see notes above.
Both Registers
E3H
E2H
E1H
E5H
E4H
EBH
EAH
E9H
EDH
ECH