PIC16F688T-I/SL Microchip Technology, PIC16F688T-I/SL Datasheet - Page 409

• Manufacturer Part Number: PIC16F688T-I/SL
• Description: IC MCU PIC FLASH 4KX14 14SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688T-I/SL

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT14SO-1 - SOCKET TRANSITION 14SOIC 150/208AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16F688T-I/SL; PIC16F688T-I/SLTR

1997 Microchip Technology Inc.
Legend C
VA
Rs
V
I
R
SS
C
LEAKAGE
PIN
T
IC
HOLD
Section 22. Basic 8-bit A/D Converter
RAx
Figure 22-3:
C
5 pF
PIN
Note 1: The reference voltage (V
Note 2: The charge holding capacitor (C
Note 3: The maximum recommended impedance for analog sources is 10 k . This is
Note 4: After a conversion has completed, a 2.0 T
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
VARIOUS JUNCTIONS
out.
required to meet the pin leakage specification.
can begin again. During this time the holding capacitor is not connected to the
selected A/D input channel.
Analog Input Model
V
DD
V
V
T
T
= 0.6V
= 0.6V
REF
I leakage
500 nA
) has no effect on the equation, since it cancels itself
R
IC
HOLD
1k
) is not discharged after each conversion.
V
SS
DD
AD
Sampling
Switch
delay must complete before acquisition
6V
5V
4V
3V
2V
R
SS
Sampling Switch
5 6 7 8 9 10 11
V
SS
C
( k )
HOLD
= 51.2 pF
DS31022A-page 22-7
22