ATTINY25-20PU Atmel, ATTINY25-20PU Datasheet - Page 121
![IC AVR MCU 2K 20MHZ 8-DIP](/photos/6/50/65033/313-8-dip_sml.jpg)
ATTINY25-20PU
Manufacturer Part Number
ATTINY25-20PU
Description
IC AVR MCU 2K 20MHZ 8-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY25-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
4
Height
3.3 mm
Length
9.27 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
6.35 mm
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 121 of 236
- Download datasheet (5Mb)
2586M–AVR–07/10
Basically only the function of the outputs are affected by these bits. Data and clock inputs are
not affected by the mode selected and will always have the same function. The counter and USI
Data Register can therefore be clocked externally and data input sampled, even when outputs
are disabled.
• Bits 3:2 – USICS[1:0]: Clock Source Select
These bits set the clock source for the USI Data Register and counter. The data output latch
ensures that the output is changed at the opposite edge of the sampling of the data input
(DI/SDA) when using external clock source (USCK/SCL). When software strobe or
Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and
therefore the output is changed immediately.
Clearing the USICS[1:0] bits enables software strobe option. When using this option, writing a
one to the USICLK bit clocks both the USI Data Register and the counter. For external clock
source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external
clocking and software clocking by the USITC strobe bit.
Table 15-2
source used for the USI Data Register and the 4-bit counter.
Table 15-2.
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the USI Data Register to shift one step and the counter
to increment by one, provided that the software clock strobe option has been selected by writing
USICS[1:0] bits to zero. The output will change immediately when the clock strobe is executed,
i.e., during the same instruction cycle. The value shifted into the USI Data Register is sampled
the previous instruction cycle.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from
a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the
USITC strobe bit as clock source for the 4-bit counter (see
The bit will be read as zero.
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.
The toggling is independent of the setting in the Data Direction Register, but if the PORT value is
to be shown on the pin the corresponding DDR pin must be set as output (to one). This feature
allows easy clock generation when implementing master devices.
USICS1
0
0
0
1
1
1
1
USICS0
shows the relationship between the USICS[1:0] and USICLK setting and clock
Relationship between the USICS[1:0] and USICLK Setting
0
0
1
0
1
0
1
USICLK
X
0
1
0
0
1
1
Clock Source
No Clock
Software clock strobe (USICLK)
Timer/Counter0 Compare Match
External, positive edge
External, negative edge
External, positive edge
External, negative edge
Table
4-bit Counter Clock Source
No Clock
Software clock strobe (USICLK)
Timer/Counter0 Compare Match
External, both edges
External, both edges
Software clock strobe (USITC)
Software clock strobe (USITC)
15-2).
121
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