ATTINY25-20PU Atmel, ATTINY25-20PU Datasheet - Page 139
![IC AVR MCU 2K 20MHZ 8-DIP](/photos/6/50/65033/313-8-dip_sml.jpg)
ATTINY25-20PU
Manufacturer Part Number
ATTINY25-20PU
Description
IC AVR MCU 2K 20MHZ 8-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY25-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
4
Height
3.3 mm
Length
9.27 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
6.35 mm
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 139 of 236
- Download datasheet (5Mb)
2586M–AVR–07/10
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a comple te description of this bit, see
on page
• Bits 3:0 – MUX[3:0]: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC. In
case of differential input (ADC0 - ADC1 or ADC2 - ADC3), gain selection is also made with these
bits. Selecting ADC2 or ADC0 as both inputs to the differential gain stage enables offset mea-
surements. Selecting the single-ended channel ADC4 enables the temperature sensor. Refer to
Table 17-4
effect until this conversion is complete (ADIF in ADCSRA is set).
Table 17-4.
1.
2.
MUX[3:0]
0101
0000
0001
0010
0100
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
For offset calibration, only.
For temperature sensor.
141.
(1)
for details. If these bits are changed during a conversion, the change will not go into
Input Channel Selections
Single Ended
ADC0 (PB5)
ADC1 (PB2)
ADC2 (PB4)
ADC3 (PB3)
ADC4
Input
GND
N/A
V
N/A
BG
(2)
See “Operation” on page 127.
Differential Input
ADC2 (PB4)
ADC2 (PB4)
ADC2 (PB4)
ADC2 (PB4)
ADC0 (PB5)
ADC0 (PB5)
ADC0 (PB5)
ADC0 (PB5)
Positive
“ADCL and ADCH – The ADC Data Register”
Differential Input
ADC2 (PB4)
ADC2 (PB4)
ADC3 (PB3)
ADC3 (PB3)
ADC0 (PB5)
ADC0 (PB5)
ADC1 (PB2)
ADC1 (PB2)
Negative
N/A
N/A
Gain
20x
20x
20x
20x
1x
1x
1x
1x
139
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