ATTINY25-20PU Atmel, ATTINY25-20PU Datasheet - Page 99
![IC AVR MCU 2K 20MHZ 8-DIP](/photos/6/50/65033/313-8-dip_sml.jpg)
ATTINY25-20PU
Manufacturer Part Number
ATTINY25-20PU
Description
IC AVR MCU 2K 20MHZ 8-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY25-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
4
Height
3.3 mm
Length
9.27 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
6.35 mm
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2586M–AVR–07/10
101
this unit useful for lower speed functions or exact timing functions with infrequent actions.
Figure 13-2. Timer/Counter 1 Synchronization Register Block Diagram.
Timer/Counter1 and the prescaler allow running the CPU from any clock source while the pres-
caler is operating on the fast 25.6 MHz PCK clock in the asynchronous mode.
The following
PCKE
CK
PCK
SYNC
MODE
ASYNC
MODE
for a detailed description on this function. Similarly, the high prescaling opportunities make
IO-registers
OCR1C
OCF1A
OCR1A
TCCR1
GTCCR
TCNT1
TOV1
Figure 13-3
1..2 PCK Delay
1..2 PCK Delay
shows the block diagram for Timer/Counter1.
S
A
Input synchronization
registers
OCR1A_SI
OCR1C_SI
TCCR1_SI
GTCCR_SI
TCNT1_SI
OCF1A_SI
TOV1_SI
1 PCK Delay
1PCK Delay
S
A
8-BIT DATABUS
Timer/Counter1
TCNT1
~1 CK Delay
~1 CK Delay
Output synchronization
registers
TCNT_SO
OCF1A_SO
TOV1_SO
No Delay
No Delay
TCNT1
OCF1A
TOV1
99
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