AT89LP4052-20SU Atmel, AT89LP4052-20SU Datasheet - Page 38

• Manufacturer Part Number: AT89LP4052-20SU
• Description: IC 8051 MCU FLASH 4K 20SOIC
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP4052-20SU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Package: 20SOIC W
• Device Core: 8051
• Family Name: AT89
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.5
38
More About Modes 2 and 3
AT89LP2052/LP4052
Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits
(LSB first), a programmable ninth data bit, and a stop bit (1). On transmit, the ninth data bit (TB8)
can be assigned the value of “0” or “1”. On receive, the ninth data bit goes into RB8 in SCON.
The baud rate is programmable to either 1/16 or 1/32 of the oscillator frequency in Mode 2.
Mode 3 may have a variable baud rate generated from Timer 1.
Figures 18-3 and 18-4
receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only
in the ninth bit of the transmit shift register.
Transmission is initiated by any instruction that uses SBUF as a destination register. The “write
to SBUF” signal also loads TB8 into the ninth bit position of the transmit shift register and flags
the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the
machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are syn-
chronized to the divide-by-16 counter, not to the “write to SBUF” signal.
The transmission begins when SEND is activated, which puts the start bit at TXD. One bit time
later, DATA is activated, which enables the output bit of the transmit shift register to TXD. The
first shift pulse occurs one bit time after that. The first shift clocks a “1” (the stop bit) into the ninth
bit position of the shift register. Thereafter, only “0”s are clocked in. Thus, as data bits shift out to
the right, “0”s are clocked in from the left. When TB8 is at the output position of the shift register,
then the stop bit is just to the left of TB8, and all positions to the left of that contain “0”s. This con-
dition flags the TX Control unit to do one last shift, then deactivate SEND and set TI. This occurs
at the 11th divide-by-16 rollover after “write to SBUF.”
Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled
at a rate of 16 times the established baud rate. When a transition is detected, the divide-by-16
counter is immediately reset, and 1FFH is written to the input shift register.
At the seventh, eighth and ninth counter states of each bit time, the bit detector samples the
value of RXD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the
value accepted during the first bit time is not 0, the receive circuits are reset and the unit contin-
ues looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift
register, and reception of the rest of the frame proceeds.
As data bits come in from the right, “1”s shift out to the left. When the start bit arrives at the left
most position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Con-
trol block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8
and to set RI is generated if, and only if, the following conditions are met at the time the final shift
pulse is generated:
If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If
both conditions are met, the received ninth data bit goes into RB8, and the first 8 data bits go
into SBUF. One bit time later, whether the above conditions were met or not, the unit continues
looking for a 1-to-0 transition at the RXD input.
Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI.
RI = 0, and
Either SM2 = 0 or the received 9th data bit = 1
show a functional diagram of the serial port in Modes 2 and 3. The
3547J–MICRO–10/09