ATTINY261-20MU Atmel, ATTINY261-20MU Datasheet - Page 122
![IC MCU AVR 2K FLASH 20MHZ 32-QFN](/photos/12/13/121309/313-32-qfn_sml.jpg)
ATTINY261-20MU
Manufacturer Part Number
ATTINY261-20MU
Description
IC MCU AVR 2K FLASH 20MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY261-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
2-Wire, SPI, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
32MLF EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY261-20MU
Manufacturer:
AVNET
Quantity:
20 000
- Current page: 122 of 242
- Download datasheet (5Mb)
12.12.10 OCR1B – Timer/Counter1 Output Compare Register B
12.12.11 OCR1C – Timer/Counter1 Output Compare Register C
12.12.12 OCR1D – Timer/Counter1 Output Compare Register D
122
ATtiny261/461/861
The output compare register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does
only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and
OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-
ing the compare event.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the
internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are
described in section
The output compare register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1, and a compare match will clear TCNT1. This register has the same function in
Normal mode and PWM modes.
Note that, if a smaller value than three is written to the Output Compare Register C, the value is
automatically replaced by three as it is a minumum value allowed to be written to this register.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the
internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are
described in section
The output compare register D is an 8-bit read/write register.
The Timer/Counter Output Compare Register D contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does
only occur if Timer/Counter1 counts to the OCR1D value. A software write that sets TCNT1 and
OCR1D to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1D after a synchronization delay follow-
ing the compare event.
Bit
0x2C (0x4C)
Read/Write
Initial value
Bit
0x2B (0x4B)
Read/Write
Initial value
Bit
0x2A (0x4A)
Read/Write
Initial value
MSB
MSB
MSB
R/W
R/W
R/W
7
0
7
1
7
0
“Accessing 10-Bit Registers” on page
“Accessing 10-Bit Registers” on page
R/W
R/W
R/W
6
0
6
1
6
0
R/W
R/W
R/W
5
0
5
1
5
0
R/W
R/W
R/W
4
0
4
1
4
0
R/W
R/W
R/W
3
0
3
1
3
0
108.
108.
R/W
R/W
R/W
2
0
2
1
2
0
R/W
R/W
R/W
1
0
1
1
1
0
LSB
R/W
LSB
R/W
LSB
R/W
0
0
0
1
0
0
2588E–AVR–08/10
OCR1D
OCR1B
OCR1C
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