ATTINY261-20MU Atmel, ATTINY261-20MU Datasheet - Page 167
![IC MCU AVR 2K FLASH 20MHZ 32-QFN](/photos/12/13/121309/313-32-qfn_sml.jpg)
ATTINY261-20MU
Manufacturer Part Number
ATTINY261-20MU
Description
IC MCU AVR 2K FLASH 20MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY261-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
2-Wire, SPI, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
32MLF EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY261-20MU
Manufacturer:
AVNET
Quantity:
20 000
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- Download datasheet (5Mb)
17.5
17.6
17.6.1
17.6.2
2588E–AVR–08/10
EEPROM Write Prevents Writing to SPMCSR
Reading Fuse and Lock Bits from Software
Reading Lock Bits from Firmware
Reading Fuse Bits from Firmware
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible for firmware to read device fuse and lock bits.
Note:
Lock bit values are returned in the destination register after an LPM instruction has been issued
within three CPU cycles after RFLB and SELFPRGEN bits have been set in SPMCSR. The
RFLB and SELFPRGEN bits automatically clear upon completion of reading the lock bits, or if no
LPM instruction is executed within three CPU cycles, or if no SPM instruction is executed within
four CPU cycles. When RFLB and SELFPRGEN are cleared LPM functions normally.
To read the lock bits, follow the below procedure:
If successful, the contents of the destination register are as follows.
See section
The algorithm for reading fuse bytes is similar to the one described above for reading lock bits,
only the addresses are different. To read the Fuse Low Byte (FLB), follow the below procedure:
If successful, the contents of the destination register are as follows.
Refer to
Bit
Rd
Bit
Rd
1. Load the Z-pointer with 0x0001.
2. Set RFLB and SELFPRGEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the lock bits from the LPM destination register.
1. Load the Z-pointer with 0x0000.
2. Set RFLB and SELFPRGEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the FLB from the LPM destination register.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro-
grammed, will be read as one.
Table 18-5 on page 172
“Program And Data Memory Lock Bits” on page 170
FLB7
7
–
7
FLB6
6
–
6
for a detailed description and mapping of the Fuse Low Byte.
FLB5
5
–
5
FLB4
4
–
4
FLB3
3
–
3
FLB2
2
–
2
for more information.
FLB1
LB2
1
1
FLB0
LB1
0
0
167
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