ATTINY261-20PU Atmel, ATTINY261-20PU Datasheet - Page 194

• Manufacturer Part Number: ATTINY261-20PU
• Description: IC MCU AVR 2K FLASH 20MHZ 20-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261-20PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: 2-Wire/SPI/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Data Rom Size: 128 B
• Height: 4.95 mm
• Length: 26.92 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.11 mm
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.8
Figure 19-6. Parallel Programming Timing, Including some General Timing Requirements
Figure 19-7. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
194
PAGEL/BS1
(DATA, XA0, XA1/BS2, PAGEL/BS1)
XA1/BS2
XTAL1
DATA
XA0
Parallel Programming Characteristics
The timing requirements shown in
ATtiny261/461/861
ADDR0 (Low Byte)
Data & Contol
LOAD ADDRESS
(LOW BYTE)
RDY/BSY
XTAL1
WR
Figure 19-6
t
t
BVPH
DVXH
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
(i.e., t
DVXH
t
XHXL
, t
t
XHXL
XLXH
t
t
t
t
, and t
XLDX
PLBX
XLWL
PLWL
XLDX
(HIGH BYTE)
LOAD DATA
t
BVWL
) also apply to loading operation.
DATA (High Byte)
t
WLWH
WLRL
t
WLBX
LOAD ADDRESS
(LOW BYTE)
ADDR1 (Low Byte)
2588E–AVR–08/10
t
WLRH