PIC18F45J10-I/P Microchip Technology, PIC18F45J10-I/P Datasheet - Page 345

• Manufacturer Part Number: PIC18F45J10-I/P
• Description: IC PIC MCU FLASH 16KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: MSSP/SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A
A/D .................................................................................... 209
Absolute Maximum Ratings .............................................. 295
AC (Timing) Characteristics .............................................. 309
Access Bank
ACKSTAT ......................................................................... 176
ACKSTAT Status Flag ...................................................... 176
ADCAL Bit ......................................................................... 216
ADCON0 Register............................................................. 209
ADCON1 Register............................................................. 209
ADCON2 Register............................................................. 209
ADDFSR ........................................................................... 284
ADDLW ............................................................................. 247
ADDULNK ......................................................................... 284
ADDWF ............................................................................. 247
ADDWFC .......................................................................... 248
ADRESH Register............................................................. 209
ADRESL Register ..................................................... 209, 212
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................. 248
ANDWF ............................................................................. 249
Assembler
Auto-Wake-up on Sync Break Character .......................... 200
B
Bank Select Register (BSR)................................................ 53
Baud Rate Generator ........................................................ 172
BC ..................................................................................... 249
BCF ................................................................................... 250
BF ..................................................................................... 176
BF Status Flag .................................................................. 176
Block Diagrams
© 2007 Microchip Technology Inc.
A/D Converter Interrupt, Configuring ........................ 213
Acquisition Requirements ......................................... 214
ADCAL Bit................................................................. 216
ADCON0 Register..................................................... 209
ADCON1 Register..................................................... 209
ADCON2 Register..................................................... 209
ADRESH Register............................................. 209, 212
ADRESL Register ..................................................... 209
Analog Port Pins, Configuring................................... 216
Associated Registers ................................................ 218
Calculating the Minimum Required Acquisition Time 214
Calibration................................................................. 216
Configuring the Module............................................. 213
Conversion Clock (T
Conversion Status (GO/DONE Bit) ........................... 212
Conversions .............................................................. 217
Converter Characteristics ......................................... 326
Operation in Power-Managed Modes ....................... 216
Selecting and Configuring Acquisition Time ............. 215
Special Event Trigger (CCP)..................................... 218
Special Event Trigger (ECCP) .................................. 132
Use of the CCP2 Trigger........................................... 218
Load Conditions for Device Timing Specifications.... 310
Parameter Symbology .............................................. 309
Temperature and Voltage Specifications .................. 310
Timing Conditions ..................................................... 310
Mapping with Indexed Literal Offset Mode.................. 65
GO/DONE Bit............................................................ 212
MPASM Assembler................................................... 292
A/D ............................................................................ 212
Analog Input Model ................................................... 213
Baud Rate Generator................................................ 172
Capture Mode Operation .......................................... 125
AD
) ............................................ 215
Preliminary
PIC18F45J10 FAMILY
BN..................................................................................... 250
BNC .................................................................................. 251
BNN .................................................................................. 251
BNOV ............................................................................... 252
BNZ .................................................................................. 252
BOR. See Brown-out Reset.
BOV .................................................................................. 255
BRA .................................................................................. 253
Break Character (12-Bit) Transmit and Receive............... 202
BRG. See Baud Rate Generator.
Brown-out Reset (BOR)...................................................... 39
BSF................................................................................... 253
BTFSC .............................................................................. 254
BTFSS .............................................................................. 254
BTG .................................................................................. 255
BZ ..................................................................................... 256
C
C Compilers
Calibration (A/D Converter) .............................................. 216
CALL................................................................................. 256
CALLW ............................................................................. 285
Capture (CCP Module) ..................................................... 125
Comparator Analog Input Model............................... 223
Comparator I/O Operating Modes ............................ 220
Comparator Output................................................... 222
Comparator Voltage Reference................................ 226
Comparator Voltage Reference Output Buffer
Compare Mode Operation ........................................ 126
Device Clock............................................................... 26
Enhanced PWM........................................................ 133
EUSART Receive ..................................................... 199
EUSART Transmit .................................................... 197
External Power-on Reset Circuit (Slow V
Fail-Safe Clock Monitor ............................................ 238
Generic I/O Port Operation......................................... 93
Interrupt Logic............................................................. 80
MSSP (I
MSSP (I
MSSP (SPI Mode) .................................................... 145
On-Chip Reset Circuit................................................. 37
PIC18F24J10/25J10................................................... 10
PIC18F44J10/45J10................................................... 11
PLL ............................................................................. 25
PORTD and PORTE (Parallel Slave Port)................ 109
PWM Operation (Simplified) ..................................... 128
Reads from Flash Program Memory .......................... 71
Single Comparator.................................................... 221
Table Read Operation ................................................ 67
Table Write Operation ................................................ 68
Table Writes to Flash Program Memory ..................... 73
Timer0 in 16-Bit Mode .............................................. 112
Timer0 in 8-Bit Mode ................................................ 112
Timer1 ...................................................................... 116
Timer1 (16-Bit Read/Write Mode)............................. 116
Timer2 ...................................................................... 122
Watchdog Timer ....................................................... 235
and On-Chip Voltage Regulator ............................... 236
Disabling in Sleep Mode............................................. 39
MPLAB C18.............................................................. 292
MPLAB C30.............................................................. 292
Associated Registers................................................ 127
CCP Pin Configuration ............................................. 125
CCPRxH:CCPRxL Registers .................................... 125
Example ........................................................... 227
Power-up) ........................................................... 39
2
2
C Master Mode)......................................... 170
C Mode)..................................................... 155
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