ATTINY28V-1PU Atmel, ATTINY28V-1PU Datasheet - Page 24
![IC MCU AVR 2K 1.2MHZ 1.8V 28-DIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATTINY28V-1PU
Manufacturer Part Number
ATTINY28V-1PU
Description
IC MCU AVR 2K 1.2MHZ 1.8V 28-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY28V-1PU
Core Processor
AVR
Core Size
8-Bit
Speed
1.2MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Maximum Clock Frequency
1.2 MHz
Number Of Programmable I/os
11
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
24
ATtiny28L/V
enable bit, INT0 in GIMSK is set (one), the MCU will jump to the interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configured
as level interrupt.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny28 and always reads as zero.
• Bit 4 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. TOV0 is
cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 in ICR and TOV0
are set (one), the Timer/Counter0 Overflow interrupt is executed.
• Bit 3..0 - Res: Reserved Bits
These bits are reserved bits in the ATtiny28 and always read as zero.
Note:
1. One should not try to use the SBI (Set Bit in I/O Register) instruction to clear individ-
ual flags in the Register. This will result in clearing all the flags in the register,
because the register is first read, then modified and finally written, thus writing ones
to all set flags. Using the CBI (Clear Bit in I/O Register) instruction on IFR will result in
clearing all bits apart from the specified bit.
1062F–AVR–07/06