ATTINY28V-1PU Atmel, ATTINY28V-1PU Datasheet - Page 4
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ATTINY28V-1PU
Manufacturer Part Number
ATTINY28V-1PU
Description
IC MCU AVR 2K 1.2MHZ 1.8V 28-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY28V-1PU
Core Processor
AVR
Core Size
8-Bit
Speed
1.2MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Maximum Clock Frequency
1.2 MHz
Number Of Programmable I/os
11
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Architectural
Overview
4
ATtiny28L/V
The fast-access register file concept contains 32 x 8-bit general-purpose working regis-
ters with a single clock cycle access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from
the register file, the operation is executed, and the result is stored back in the register
file – in one clock cycle.
Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This
pointer is called the Z-pointer and can address the register file and the Flash program
memory.
Figure 3. The ATtiny28 AVR RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 3
shows the ATtiny28 AVR RISC microcontroller architecture. The AVR uses a Harvard
architecture concept – with separate memories and buses for program and data memo-
ries. The program memory is accessed with a two-stage pipeline. While one instruction
is being executed, the next instruction is pre-fetched from the program memory. This
concept enables instructions to be executed every clock cycle. The program memory is
reprogrammable Flash memory.
With the relative jump and relative call instructions, the whole 1K address space is
directly accessed. All AVR instructions have a single 16-bit word format, meaning that
every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subrou-
tines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions such as
Control Registers, Timer/Counters and other I/O functions. The memory spaces in the
AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a sepa-
Control Lines
Instruction
Instruction
Program
Register
Decoder
1K x 16
Flash
Program
Counter
Data Bus 8-bit
Registrers
and Test
Purpose
General
Status
32 x 8
ALU
Z
Timer/Counter
Comparator
Registrers
Watchdog
Interrupts
I/O Lines
Control
1062F–AVR–07/06
Analog
Timer
8-bit
Unit
20