ATTINY28V-1PU Atmel, ATTINY28V-1PU Datasheet - Page 37
![IC MCU AVR 2K 1.2MHZ 1.8V 28-DIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATTINY28V-1PU
Manufacturer Part Number
ATTINY28V-1PU
Description
IC MCU AVR 2K 1.2MHZ 1.8V 28-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY28V-1PU
Core Processor
AVR
Core Size
8-Bit
Speed
1.2MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Maximum Clock Frequency
1.2 MHz
Number Of Programmable I/os
11
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Watchdog Timer
Register Description
Watchdog Timer Control
Register – WDTCR
1062F–AVR–07/06
The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the
Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in
Table 15. See characterization data for typical values at other V
(Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle
periods can be selected to determine the reset period. If the reset period expires without
another Watchdog reset, the ATtiny28 resets and executes from the reset vector. For
timing details on the Watchdog reset, refer to page 18.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be
followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 30. Watchdog Timer
• Bits 7..5 - Res: Reserved Bits
These bits are reserved bits in the ATtiny28 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will
not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.
Refer to the description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one), the Watchdog Timer is enabled and if the WDE is cleared
(zero), the Watchdog Timer function is disabled. WDE can only be cleared if the
WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce-
dure must be followed:
Bit
$01
Read/Write
Initial Value
R
7
–
0
Oscillator
350 kHz at V
110 kHz at V
1 MHz at V
R
6
–
0
CC
CC
CC
= 5V
= 3V
= 2V
R
5
–
0
WDTOE
R/W
4
0
WDE
R/W
3
0
WDP2
R/W
2
0
WDP1
ATtiny28L/V
R/W
1
0
CC
levels. The WDR
WDP0
R/W
0
0
WDTCR
37