PIC18LF24J50-I/ML Microchip Technology, PIC18LF24J50-I/ML Datasheet - Page 146
![IC PIC MCU FLASH 16K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF24J50-I/ML
Manufacturer Part Number
PIC18LF24J50-I/ML
Description
IC PIC MCU FLASH 16K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF24J50-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, MA180024, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F46J50 FAMILY
9.7.3.3
The control schema of the PPS is extremely flexible.
Other than systematic blocks that prevent signal con-
tention caused by two physical pins being configured
as the same functional input or two functional outputs
configured as the same pin, there are no hardware
enforced lock outs. The flexibility extends to the point of
allowing a single input to drive multiple peripherals or a
single functional output to drive multiple output pins.
9.7.4
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC18F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
9.7.4.1
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these reg-
isters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (PPSCON<0>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
2.
3.
IOLOCK remains in one state until changed. This
allows all of the PPS registers to be configured with a
single unlock sequence followed by an update to all
control registers, then locked with a second lock
sequence.
9.7.4.2
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
DS39931C-page 146
Write 55h to EECON2<7:0>.
Write AAh to EECON2<7:0>.
Clear (or set) IOLOCK as a single operation.
CONTROLLING CONFIGURATION
CHANGES
Mapping Limitations
Control Register Lock
Continuous State Monitoring
9.7.4.3
As an additional level of safety, the device can be con-
figured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY
(CONFIG3H<0>) Configuration bit blocks the IOLOCK
bit from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute and the PPS control registers cannot be
written to. The only way to clear the bit and re-enable
peripheral remapping is to perform a device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the PPS
registers.
9.7.5
The ability to control peripheral pin selection introduces
several considerations into application design that
could be overlooked. This is particularly true for several
common peripherals that are available only as
remappable peripherals.
The main consideration is that the PPS is not available
on default pins in the device’s default (Reset) state.
Since all RPINRx registers reset to ‘11111’ and all
RPORx registers reset to ‘00000’, all PPS inputs are
tied to RP31 and all PPS outputs are disconnected.
This situation requires the user to initialize the device
with the proper peripheral configuration before any
other application code is executed. Since the IOLOCK
bit resets in the unlocked state, it is not necessary to
execute the unlock sequence after the device has
come out of Reset.
For application safety, however, it is best to set
IOLOCK and lock the configuration after writing to the
control registers.
The unlock sequence is timing critical. Therefore, it is
recommended that the unlock sequence be executed
as an assembly language routine with interrupts
temporarily disabled. If the bulk of the application is
written in C or another high-level language, the unlock
sequence should be performed by writing in-line
assembly.
Note:
CONSIDERATIONS FOR
PERIPHERAL PIN SELECTION
In tying PPS inputs to RP31, RP31 does
not have to exist on a device for the
registers to be reset to it.
Configuration Bit Pin Select Lock
© 2009 Microchip Technology Inc.
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