PIC18LF24J50-I/ML Microchip Technology, PIC18LF24J50-I/ML Datasheet - Page 207
![IC PIC MCU FLASH 16K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF24J50-I/ML
Manufacturer Part Number
PIC18LF24J50-I/ML
Description
IC PIC MCU FLASH 16K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF24J50-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, MA180024, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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14.0
The Timer3 timer/counter module incorporates these
features:
• Software selectable operation as a 16-bit timer or
• Readable and writable 8-bit registers (TMR3H
• Selectable clock source (internal or external) with
• Interrupt-on-overflow
• Module Reset on ECCP Special Event Trigger
REGISTER 14-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Note 1:
TMR3CS1
counter
and TMR3L)
device clock or Timer1 oscillator internal options
R/W-0
2:
TIMER3 MODULE
The F
The Timer1 oscillator crystal driver is powered whenever T1OSCEN (T1CON) or T3OSCEN (T3CON) = 1.
The circuit is enabled by the logical OR of these two bits. When disabled, the inverter and feedback resistor
are disabled to eliminate power drain. The TMR1ON and TMR3ON bits do not have to be enabled to power
up the crystal driver.
TMR3CS<1:0>: Timer3 Clock Source Select bits
10 = Timer3 clock source is the Timer1 oscillator or the T3CKI digital input pin (assigned in PPS module)
01 = Timer3 clock source is the system clock (F
00 = Timer3 clock source is the instruction clock (F
T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
T3OSCEN: Timer3 Oscillator Source Select bit
When TMR3CS<1:0> = 10:
1 = Power up the Timer1 crystal driver (T1OSC) and supply the Timer3 clock from the crystal output
0 = Timer1 crystal driver off
When TMR3CS<1:0> = 0x:
1 = Power up the Timer1 crystal driver (T1OSC)
0 = Timer1 crystal driver off
T3SYNC: Timer3 External Clock Input Synchronization Control bit
When TMR3CS<1:0> = 10:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS<1:0> = 0x:
This bit is ignored; Timer3 uses the internal clock.
RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
TMR3CS0
OSC
R/W-0
clock source should not be selected if the timer will be used with the ECCP capture/compare features.
T3CON: TIMER3 CONTROL REGISTER (ACCESS F79h)
W = Writable bit
‘1’ = Bit is set
T3CKPS1
R/W-0
(2)
(2)
, Timer3 clock is from the T3CKI digital input pin assigned in PPS module
T3CKPS0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F46J50 FAMILY
T3OSCEN
A simplified block diagram of the Timer3 module is
shown in Figure 14-1.
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the ECCP modules; see Section 17.1.1
“ECCP Module and Timer Resources” for more
information.
The F
be used with the ECCP capture/compare features. If the
timer will be used with the capture or compare features,
always select one of the other timer clocking options.
OSC
R/W-0
OSC
)
(1)
OSC
/4)
clock source (TMR3CS<1:0> = 01) should not
T3SYNC
R/W-0
x = Bit is unknown
R/W-0
RD16
DS39931C-page 207
TMR3ON
R/W-0
bit 0
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