AT90USB82-16MU Atmel, AT90USB82-16MU Datasheet - Page 218

• Manufacturer Part Number: AT90USB82-16MU
• Description: IC AVR MCU 8K FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB82-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Controller Family/series: AVR USB
• No. Of I/o's: 22
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Package: 32QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

218
AT90USB82/162
• 0 - TXINI - Transmitter Ready Interrupt Flag
Set by hardware to signal that the current bank is free and can be filled. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
This bit is inactive (cleared) if the endpoint is an OUT endpoint.
• 7 - FLERRE - Flow Error Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
• 6 - NAKINE - NAK IN Interrupt Enable Bit
Set to enable an endpoint interrupt (EPINTx) when NAKINI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKINI is set.
• 5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - NAKOUTE - NAK OUT Interrupt Enable Bit
Set to enable an endpoint interrupt (EPINTx) when NAKOUTI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKOUTI is set.
• 3 - RXSTPE - Received SETUP Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when RXSTPI is sent.
Clear to disable an endpoint interrupt (EPINTx) when RXSTPI is sent.
• 2 - RXOUTE - Received OUT Data Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when RXOUTI is sent.
Clear to disable an endpoint interrupt (EPINTx) when RXOUTI is sent.
• 1 - STALLEDE - Stalled Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when STALLEDI is sent.
Clear to disable an endpoint interrupt (EPINTx) when STALLEDI is sent.
• 0 - TXINE - Transmitter Ready Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when TXINI is sent.
Clear to disable an endpoint interrupt (EPINTx) when TXINI is sent.
Bit
Read/Wri
te
Initial
Value
7
FLERRE
R/W
0
6
NAKINE
R/W
0
5
-
R
0
4
NAKOUTE
R/W
0
3
RXSTPE
R/W
0
2
RXOUTE
R/W
0
1
STALLEDE
R/W
0
0
TXINE
R/W
0
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UEIENX