PIC18F1220-I/P Microchip Technology, PIC18F1220-I/P Datasheet - Page 5

• Manufacturer Part Number: PIC18F1220-I/P
• Description: IC MCU FLASH 2KX16 A/D 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-I/P

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Package: 18PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP180 - DEVICE ADAPTER 18F1320 PDIP 18LDACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.3
For the PIC18F1330 device, the code memory
space extends from 00000h to 01FFFh (8 Kbytes) in
two 4-Kbyte blocks. For the PIC18F1230 device, the
code memory space extends from 00000h to 00FFFh
(4 Kbytes) in two 2-Kbyte blocks. Addresses 00000h
through 07FFh, however, define a “Boot Block” region
that is treated separately from Block 0. All of these
blocks define code protection boundaries within the
code memory space.
FIGURE 2-4:
© 2009 Microchip Technology Inc.
Memory Maps
Note:
000000h
01FFFFh
200000h
3FFFFFh
*
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L.
MEMORY MAP AND CODE MEMORY SPACE FOR THE PIC18F1230 DEVICE
Unimplemented
Code Memory
Configuration
Read as ‘0’
and ID
Space
MEMORY SIZE/DEVICE
Unimplemented
(PIC18F1230)
The size of the Boot Block in PIC18F1230/1330
devices can be configured as 256, 512 or 1K words.
This is done through the BBSIZ<1:0> bits in the
Configuration register, CONFIG4L (see Table 5-1). It is
important to note that increasing the size of the Boot
Block decreases the size of Block 0.
TABLE 2-2:
Boot Block
4 Kbytes
Read ‘0’s
Block 0
Block 1
PIC18F1230
PIC18F1330
Device
PIC18F1230/1330
IMPLEMENTATION OF CODE
MEMORY
000000h
0001FFh* or 0003FFh*
000200h* or 000400h
0007FFh
000800h
000FFFh
001000h
01FFFFh
Address
Range
Code Memory Size (Bytes)
00000h-00FFFh (4K)
00000h-01FFFh (8K)
DS39752B-page 5